The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une méthode de génération de HDL synthétisable pour les processeurs pipeline est proposée. Grâce au procédé proposé, des descriptions de chemin de données et de logique de commande d'un processeur cible sont générées à partir d'une spécification de jeu d'instructions basée sur une horloge. À partir des résultats expérimentaux, la faisabilité de la méthode proposée est évaluée et le temps de conception du processeur a été considérablement réduit par rapport à celui de la conception manuelle conventionnelle au niveau RT en HDL.
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Makiko ITOH, Yoshinori TAKEUCHI, Masaharu IMAI, Akichika SHIOMI, "Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 3, pp. 394-400, March 2000, doi: .
Abstract: A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_3_394/_p
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@ARTICLE{e83-a_3_394,
author={Makiko ITOH, Yoshinori TAKEUCHI, Masaharu IMAI, Akichika SHIOMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description},
year={2000},
volume={E83-A},
number={3},
pages={394-400},
abstract={A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 394
EP - 400
AU - Makiko ITOH
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
AU - Akichika SHIOMI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2000
AB - A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.
ER -