The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une PLL CMOS (boucle à verrouillage de phase) de 3.3 V avec un VCO (oscillateur contrôlé en tension) à retour automatique est conçue pour les applications haute fréquence, basse tension et faible consommation. Cet article propose une nouvelle architecture PLL pour améliorer la linéarité tension-fréquence du VCO avec une nouvelle cellule à retard. Le VCO proposé avec un chemin d'auto-rétroaction fonctionne sur une large gamme de fréquences de 30 MHz à 1 GHz avec une bonne linéarité. Le convertisseur de tension DC-DC Up/Down est nouvellement conçu pour réguler la tension de commande du VCO à deux étages. L'architecture PLL conçue est implémentée sur un processus CMOS à puits n de 0.6 µm. Les résultats de la simulation illustrent un temps de verrouillage de 2.6 µs à 1 GHz, un verrouillage dans la plage de 100 MHz à 1 GHz et une dissipation de puissance de 112 mW.
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Yeon Kug MOON, Kwang Sub YOON, "A 3.3 V CMOS PLL with a Self-Feedback VCO" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2623-2626, December 2000, doi: .
Abstract: A 3.3 V CMOS PLL (Phase Locked loop) with a self-feedback VCO (Voltage Controlled Oscillator) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO with a new delay cell. The proposed VCO with a self-feedback path operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC Voltage Up/Down Converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 µm n-well CMOS process. The simulation results illustrate a locking time of 2.6 µsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112 mW.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2623/_p
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@ARTICLE{e83-a_12_2623,
author={Yeon Kug MOON, Kwang Sub YOON, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 3.3 V CMOS PLL with a Self-Feedback VCO},
year={2000},
volume={E83-A},
number={12},
pages={2623-2626},
abstract={A 3.3 V CMOS PLL (Phase Locked loop) with a self-feedback VCO (Voltage Controlled Oscillator) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO with a new delay cell. The proposed VCO with a self-feedback path operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC Voltage Up/Down Converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 µm n-well CMOS process. The simulation results illustrate a locking time of 2.6 µsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112 mW.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A 3.3 V CMOS PLL with a Self-Feedback VCO
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2623
EP - 2626
AU - Yeon Kug MOON
AU - Kwang Sub YOON
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - A 3.3 V CMOS PLL (Phase Locked loop) with a self-feedback VCO (Voltage Controlled Oscillator) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO with a new delay cell. The proposed VCO with a self-feedback path operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC Voltage Up/Down Converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 µm n-well CMOS process. The simulation results illustrate a locking time of 2.6 µsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112 mW.
ER -