The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, nous proposons une méthode de synthèse cellulaire pour un procédé Salicide. Notre méthode utilise l'interconnexion locale entre transistors adjacents, disponible dans certains processus Salicide, et optimise le placement des transistors d'une cellule en tenant compte à la fois de la surface et du nombre d'interconnexions locales. De cette façon, nous réduisons le nombre de fils et de contacts métalliques. Le modèle de circuit ne se limite pas à la logique CMOS série-parallèle conventionnelle, et notre méthode nous permet de synthétiser des circuits à transistors passants CMOS. Les résultats expérimentaux montrent que notre méthode utilise efficacement l’interconnexion locale et optimise à la fois la surface des cellules et la longueur du fil métallique.
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Kazuhisa OKADA, Takayuki YAMANOUCHI, Takashi KAMBE, "A Cell Synthesis Method for Salicide Process Using Assignment Graph" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2577-2583, December 2000, doi: .
Abstract: In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2577/_p
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@ARTICLE{e83-a_12_2577,
author={Kazuhisa OKADA, Takayuki YAMANOUCHI, Takashi KAMBE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Cell Synthesis Method for Salicide Process Using Assignment Graph},
year={2000},
volume={E83-A},
number={12},
pages={2577-2583},
abstract={In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Cell Synthesis Method for Salicide Process Using Assignment Graph
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2577
EP - 2583
AU - Kazuhisa OKADA
AU - Takayuki YAMANOUCHI
AU - Takashi KAMBE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.
ER -