The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les circuits logiques combinatoires sont généralement mis en œuvre sous forme de réseaux de nœuds logiques à plusieurs niveaux. La simplification logique multi-niveaux utilisant la fonction « ne s'en soucie pas » sur chaque nœud est largement utilisée. Les grandes valeurs ne s'en soucient pas donnent de bons résultats de simplification, mais souffrent d'une zone mémoire et d'un temps de calcul énormes. L'extraction des indifférents utiles et la réduction de la taille des indifférents sont des problèmes importants lors de la simplification à l'aide de l'inquiétant. Dans cet article, nous proposons une nouvelle méthode heuristique robuste pour la sélection des indifférents. Nous considérons un sous-réseau adaptatif pour chaque nœud simplifié du réseau et introduisons une méthode d'amélioration par étapes du sous-réseau prenant en compte la zone mémoire et la structure du réseau. Les indifférents extraits des sous-réseaux adaptatifs sont appelés les indifférents locaux. Nous avons implémenté notre méthode pour que la satisfiabilité s'en fiche et que l'observabilité s'en fiche. Nous avons appliqué la méthode sur des benchmarks MCNC89, et comparé les résultats expérimentaux avec ceux du système SIS. Les résultats démontrent la supériorité de notre méthode sur la qualité des résultats et sur la taille des circuits applicables.
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Qiang ZHU, Yusuke MATSUNAGA, Shinji KIMURA, Katsumasa WATANABE, "Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2520-2527, December 2000, doi: .
Abstract: Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2520/_p
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@ARTICLE{e83-a_12_2520,
author={Qiang ZHU, Yusuke MATSUNAGA, Shinji KIMURA, Katsumasa WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure},
year={2000},
volume={E83-A},
number={12},
pages={2520-2527},
abstract={Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2520
EP - 2527
AU - Qiang ZHU
AU - Yusuke MATSUNAGA
AU - Shinji KIMURA
AU - Katsumasa WATANABE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.
ER -