The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente une technique évolutive pour construire et maintenir des circuits numériques récupérables après panne. La synthèse d'un circuit par algorithme génétique progressant en fonction des objectifs comportementaux du circuit et des interactions avec les environnements, la connaissance de l'architecture ainsi que des processus de placement et de routage n'est pas la préoccupation majeure de la méthode proposée. Le comportement évolutif du circuit empêche également le circuit de rester coincé dans des défauts en modifiant continuellement les blocs de circuit voisins en conséquence. Cela se fait sans savoir au préalable où et comment les défauts se produisent en raison de leur nature évolutive. Ainsi, les blocs de circuits généraux pour le diagnostic des pannes et la redondance sont minimisés grâce à cette conception. Les circuits matériels évolutifs récupérables sur panne sont synthétisés pour construire quelques logiques combinatoires par évolution et les capacités de récupération sur panne sont présentées avec le FPGA reconfigurable.
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Tae-Suh PARK, Chong-Ho LEE, Duck-Jin CHUNG, "Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2488-2497, December 2000, doi: .
Abstract: This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2488/_p
Copier
@ARTICLE{e83-a_12_2488,
author={Tae-Suh PARK, Chong-Ho LEE, Duck-Jin CHUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit},
year={2000},
volume={E83-A},
number={12},
pages={2488-2497},
abstract={This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.},
keywords={},
doi={},
ISSN={},
month={December},}
Copier
TY - JOUR
TI - Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2488
EP - 2497
AU - Tae-Suh PARK
AU - Chong-Ho LEE
AU - Duck-Jin CHUNG
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.
ER -