The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente une technique de validation d'architecture de bus au niveau système et montre son application à la conception d'un produit grand public. Cette technique permet de valider l'ensemble du système avec une précision de cycle de bus à l'aide de modèles de niveau d'architecture de bus dérivés de leurs modèles de niveau comportemental correspondants. Les résultats expérimentaux issus de la conception d'un système d'appareil photo numérique (DSC) montrent que notre approche offre une vitesse de simulation beaucoup plus rapide que les simulateurs de niveau de transfert de registre (RTL). Grâce à cette technique de validation rapide et précise, les conceptions, validations et optimisations d'architecture de bus peuvent être réalisées efficacement au niveau du système et le temps total d'exécution des conceptions de systèmes peut être considérablement réduit.
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Kazuyoshi TAKEMURA, Masanobu MIZUNO, Akira MOTOHARA, "A Practical Method for System-Level Bus Architecture Validation" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2439-2445, December 2000, doi: .
Abstract: This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera (DSC) system design show that our approach offers much faster simulation speed than register transfer level (RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2439/_p
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@ARTICLE{e83-a_12_2439,
author={Kazuyoshi TAKEMURA, Masanobu MIZUNO, Akira MOTOHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Practical Method for System-Level Bus Architecture Validation},
year={2000},
volume={E83-A},
number={12},
pages={2439-2445},
abstract={This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera (DSC) system design show that our approach offers much faster simulation speed than register transfer level (RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Practical Method for System-Level Bus Architecture Validation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2439
EP - 2445
AU - Kazuyoshi TAKEMURA
AU - Masanobu MIZUNO
AU - Akira MOTOHARA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera (DSC) system design show that our approach offers much faster simulation speed than register transfer level (RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.
ER -