The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
À mesure que la fonction d'un système devient de plus en plus complexe, la réutilisation de la propriété intellectuelle (propriété intellectuelle) est la tendance dans le style de conception du système. Les concepteurs doivent évaluer les performances et les fonctionnalités de chaque bloc IP candidat pouvant être utilisé dans leur conception, tandis que les fournisseurs IP espèrent garder secrète la structure de leurs blocs IP. Un modèle de puissance au niveau IP est un modèle qui prend uniquement les statistiques d'entrée primaires comme paramètres et ne révèle aucune information sur la taille des transistors ou la structure du circuit. Cet article propose une nouvelle méthode pour construire un modèle de puissance adapté aux blocs de circuits de niveau IP. Il s'agit d'une méthode de sélection de points nominaux pour les modèles de puissance basée sur les sensibilités de puissance. En analysant la relation entre la consommation d'énergie dynamique des circuits CMOS et les statistiques de leurs signaux d'entrée, une ligne directrice pour la sélection du point nominal est proposée. À partir de notre analyse, le premier point nominal est sélectionné pour minimiser l'erreur d'estimation moyenne et deux autres points nominaux sont sélectionnés pour minimiser l'erreur d'estimation maximale. Nos résultats expérimentaux sur un certain nombre de circuits de référence montrent l'efficacité de la méthode proposée. Une précision d'estimation moyenne de 5.78 % des simulations au niveau du transistor est obtenue. La méthode proposée peut être appliquée pour créer un environnement d’estimation de puissance au niveau du système sans révéler le contenu des blocs IP à l’intérieur. Il s’agit donc d’une méthode prometteuse pour la construction de modèles de puissance au niveau IP.
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Heng-Liang HUANG, Jiing-Yuan LIN, Wen-Zen SHEN, Jing-Yang JOU, "A New Method for Constructing IP Level Power Model Based on Power Sensitivity" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2431-2438, December 2000, doi: .
Abstract: As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2431/_p
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@ARTICLE{e83-a_12_2431,
author={Heng-Liang HUANG, Jiing-Yuan LIN, Wen-Zen SHEN, Jing-Yang JOU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Method for Constructing IP Level Power Model Based on Power Sensitivity},
year={2000},
volume={E83-A},
number={12},
pages={2431-2438},
abstract={As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.},
keywords={},
doi={},
ISSN={},
month={December},}
Copier
TY - JOUR
TI - A New Method for Constructing IP Level Power Model Based on Power Sensitivity
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2431
EP - 2438
AU - Heng-Liang HUANG
AU - Jiing-Yuan LIN
AU - Wen-Zen SHEN
AU - Jing-Yang JOU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.
ER -