The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un circuit intégré à courant commuté, qui réalise le modèle de neurone chaotique, est présenté. Le circuit se compose principalement d'inverseurs CMOS utilisés comme amplificateurs de transconductance et éléments non linéaires. La puce a été fabriquée à l'aide d'un procédé HP CMOS de 1.2 µm. Une seule cellule neuronale occupe seulement 0.0076 mm2, ce qui représente une surface plus petite que celle occupée par un plot de liaison standard. Le fonctionnement du circuit a été testé à une fréquence d'horloge de 2 MHz.
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Ruben HERRERA, Ken SUYAMA, Yoshihiko HORIO, Kazuyuki AIHARA, "IC Implementation of a Switched-Current Chaotic Neuron" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 9, pp. 1776-1782, September 1999, doi: .
Abstract: A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 µm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_9_1776/_p
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@ARTICLE{e82-a_9_1776,
author={Ruben HERRERA, Ken SUYAMA, Yoshihiko HORIO, Kazuyuki AIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={IC Implementation of a Switched-Current Chaotic Neuron},
year={1999},
volume={E82-A},
number={9},
pages={1776-1782},
abstract={A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 µm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.},
keywords={},
doi={},
ISSN={},
month={September},}
Copier
TY - JOUR
TI - IC Implementation of a Switched-Current Chaotic Neuron
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1776
EP - 1782
AU - Ruben HERRERA
AU - Ken SUYAMA
AU - Yoshihiko HORIO
AU - Kazuyuki AIHARA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 1999
AB - A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 µm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.
ER -