The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente un algorithme heuristique qui minimise le retard d'un circuit donné grâce à une sélection de cellule en deux passes dans une conception basée sur les cellules. Tout d’abord, nous introduisons un nouveau graphe, appelé site Web des candidats, qui représente commodément toutes les combinaisons de cellules disponibles pour la mise en œuvre du circuit donné. Nous présentons ensuite une méthode efficace pour obtenir un ensemble provisoire de cellules optimales, tout en estimant le délai du chemin le plus long entre chaque cellule et la sortie principale sur le réseau candidat. Dans cette étape, plusieurs cellules sont autorisées à lier la même porte logique. Enfin, nous décrivons comment l'approche proposée sélectionne réellement les cellules optimales dans l'ensemble provisoire, ce qui minimiserait le retard du circuit. Les résultats expérimentaux sur un ensemble de tests montrent que l'approche proposée est efficace et efficiente pour minimiser le retard du circuit donné.
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Tae Hoon KIM, Young Hwan KIM, "DEMI: A Delay Minimization Algorithm for Cell-Based Digital VLSI Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 3, pp. 504-511, March 1999, doi: .
Abstract: This paper presents a heuristic algorithm that minimizes the delay of the given circuit through a two-pass cell selection in cell-based design. First, we introduce a new graph, called candidate web, which conveniently represents all cell combinations available for the implementation of the given circuit. We, then, present an efficient method to obtain a tentative set of optimal cells, while estimating the delay of the longest path between each cell and the primary output on the candidate web. In this step, multiple cells are allowed to bind the same logic gate. Finally, we describe how the proposed approach actually selects the optimal cells from the tentative set, which would minimize the circuit delay. Experimental results on a set of benchmarks show that the proposed approach is effective and efficient in minimizing the delay of the given circuit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_3_504/_p
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@ARTICLE{e82-a_3_504,
author={Tae Hoon KIM, Young Hwan KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={DEMI: A Delay Minimization Algorithm for Cell-Based Digital VLSI Design},
year={1999},
volume={E82-A},
number={3},
pages={504-511},
abstract={This paper presents a heuristic algorithm that minimizes the delay of the given circuit through a two-pass cell selection in cell-based design. First, we introduce a new graph, called candidate web, which conveniently represents all cell combinations available for the implementation of the given circuit. We, then, present an efficient method to obtain a tentative set of optimal cells, while estimating the delay of the longest path between each cell and the primary output on the candidate web. In this step, multiple cells are allowed to bind the same logic gate. Finally, we describe how the proposed approach actually selects the optimal cells from the tentative set, which would minimize the circuit delay. Experimental results on a set of benchmarks show that the proposed approach is effective and efficient in minimizing the delay of the given circuit.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - DEMI: A Delay Minimization Algorithm for Cell-Based Digital VLSI Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 504
EP - 511
AU - Tae Hoon KIM
AU - Young Hwan KIM
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1999
AB - This paper presents a heuristic algorithm that minimizes the delay of the given circuit through a two-pass cell selection in cell-based design. First, we introduce a new graph, called candidate web, which conveniently represents all cell combinations available for the implementation of the given circuit. We, then, present an efficient method to obtain a tentative set of optimal cells, while estimating the delay of the longest path between each cell and the primary output on the candidate web. In this step, multiple cells are allowed to bind the same logic gate. Finally, we describe how the proposed approach actually selects the optimal cells from the tentative set, which would minimize the circuit delay. Experimental results on a set of benchmarks show that the proposed approach is effective and efficient in minimizing the delay of the given circuit.
ER -