The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, nous proposons une méthode d'accélération du temps de commutation de fréquence dans le synthétiseur de fréquence à boucle à verrouillage de phase (PLL) utilisant le détecteur de fréquence cible (TFD). Le TFD détecte l'heure Ta pour tous les canaux où la sortie du synthétiseur de fréquence PLL atteint la fréquence cible pour la première fois. À Ta, le diviseur programmable, le diviseur de référence et le comparateur de phase sont réinitialisés, et la phase du synthétiseur de fréquence PLL est initialisée et la synchronisation de phase est obtenue. Dans la méthode proposée, puisque la sonnerie dans l'état transitoire ne se produit pas, la sortie du synthétiseur de fréquence PLL converge vers la fréquence cible à Ta et le temps de commutation de fréquence est accéléré. L'efficacité de la méthode proposée sera confirmée par des résultats expérimentaux.
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Shigeki OBOTE, Yasuaki SUMI, Naoki KITAI, Kouichi SYOUBU, Yutaka FUKUI, Yoshio ITOH, "Speedup of Frequency Switching Time in PLL Frequency Synthesizers Using a Target Frequency Detector" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 3, pp. 436-441, March 1999, doi: .
Abstract: In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are reset, and the phase of the PLL frequency synthesizer is initialized and the phase synchronization is achieved. In the proposed method, since the ringing in the transient state does not occur, the output of the PLL frequency synthesizer converges to the target frequency at Ta and the frequency switching time is speeded up. The effectiveness of the proposed method will be confirmed by experimental results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_3_436/_p
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@ARTICLE{e82-a_3_436,
author={Shigeki OBOTE, Yasuaki SUMI, Naoki KITAI, Kouichi SYOUBU, Yutaka FUKUI, Yoshio ITOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Speedup of Frequency Switching Time in PLL Frequency Synthesizers Using a Target Frequency Detector},
year={1999},
volume={E82-A},
number={3},
pages={436-441},
abstract={In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are reset, and the phase of the PLL frequency synthesizer is initialized and the phase synchronization is achieved. In the proposed method, since the ringing in the transient state does not occur, the output of the PLL frequency synthesizer converges to the target frequency at Ta and the frequency switching time is speeded up. The effectiveness of the proposed method will be confirmed by experimental results.},
keywords={},
doi={},
ISSN={},
month={March},}
Copier
TY - JOUR
TI - Speedup of Frequency Switching Time in PLL Frequency Synthesizers Using a Target Frequency Detector
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 436
EP - 441
AU - Shigeki OBOTE
AU - Yasuaki SUMI
AU - Naoki KITAI
AU - Kouichi SYOUBU
AU - Yutaka FUKUI
AU - Yoshio ITOH
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1999
AB - In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are reset, and the phase of the PLL frequency synthesizer is initialized and the phase synchronization is achieved. In the proposed method, since the ringing in the transient state does not occur, the output of the PLL frequency synthesizer converges to the target frequency at Ta and the frequency switching time is speeded up. The effectiveness of the proposed method will be confirmed by experimental results.
ER -