The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose un nouveau multiplicateur analogique CMOS. Son principal avantage est qu'il est exempt de réduction de mobilité et d'effet corporel. Ainsi, le multiplicateur proposé devrait avoir une bonne linéarité, par rapport aux multiplicateurs conventionnels. Quatre transistors fonctionnant dans la région linéaire constituent la cellule d'entrée du multiplicateur. Leurs sources et backgates sont reliées au sol pour annuler l’effet de corps. eLeurs grilles sont fixées à la même tension de polarisation pour supprimer l'effet de réduction de mobilité. Les signaux d'entrée sont appliqués aux drains des transistors de la cellule d'entrée via des nulleurs modifiés. Les résultats de simulation montrent que le THD est inférieur à 0.8% pour 0.6 V pp signal d'entrée à une tension d'alimentation de 2.5 V et que la bande passante de 3 dB atteint environ 13.3 MHz.
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Eitake IBARAGI, Akira HYOGO, Keitaro SEKINE, "A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 2, pp. 327-334, February 1999, doi: .
Abstract: This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_327/_p
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@ARTICLE{e82-a_2_327,
author={Eitake IBARAGI, Akira HYOGO, Keitaro SEKINE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect},
year={1999},
volume={E82-A},
number={2},
pages={327-334},
abstract={This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.},
keywords={},
doi={},
ISSN={},
month={February},}
Copier
TY - JOUR
TI - A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 327
EP - 334
AU - Eitake IBARAGI
AU - Akira HYOGO
AU - Keitaro SEKINE
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.
ER -