The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
La conception de circuits hautes performances utilisant des FPGA (Field-Programmable Gate Arrays) nécessite un équilibre entre l'architecture du FPGA et les algorithmes de CAO. Les FPGA et les algorithmes CAO conventionnels sont développés indépendamment, ce qui rend difficile la mise en œuvre de circuits d'application. Pour résoudre ce problème, nous avons développé un FPGA vérifié en CAO dont l'architecture a été conçue en même temps que les algorithmes de CAO. Cet article montre comment une architecture FPGA vérifiée par CAO peut simplifier un algorithme de routage. L'algorithme est étudié en termes de complexité de calcul et est simplifié grâce aux propriétés de notre FPGA (structure des modules de commutation et nombre de ressources de routage). L'algorithme de routage est presque cent fois plus rapide que celui du routeur classique, et la qualité de ses circuits est également améliorée.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Takahiro MUROOKA, Atsushi TAKAHARA, Toshiaki MIYAZAKI, "Simplified Routing Procedure for a CAD-Verified FPGA" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2440-2447, November 1999, doi: .
Abstract: The design of high performance-circuits using Field-Programmable Gate Arrays (FPGAs) requires a balance between the FPGA's architecture and CAD algorithms. Conventional FPGAs and CAD algorithms are developed independently, which makes it difficult to implement application circuits. To solve this problem, we developed a CAD-verified FPGA whose architecture was designed at the same time as the CAD algorithms. This paper shows how a CAD-verified FPGA architecture can simplify a routing algorithm. The algorithm is studied in terms of computational complexity and is simplified using the properties of our FPGA (switch module structure and the number of routing resources). The routing algorithm is almost one hundred times faster than that of the conventional router, and the quality of its circuits is also improved.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2440/_p
Copier
@ARTICLE{e82-a_11_2440,
author={Takahiro MUROOKA, Atsushi TAKAHARA, Toshiaki MIYAZAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Simplified Routing Procedure for a CAD-Verified FPGA},
year={1999},
volume={E82-A},
number={11},
pages={2440-2447},
abstract={The design of high performance-circuits using Field-Programmable Gate Arrays (FPGAs) requires a balance between the FPGA's architecture and CAD algorithms. Conventional FPGAs and CAD algorithms are developed independently, which makes it difficult to implement application circuits. To solve this problem, we developed a CAD-verified FPGA whose architecture was designed at the same time as the CAD algorithms. This paper shows how a CAD-verified FPGA architecture can simplify a routing algorithm. The algorithm is studied in terms of computational complexity and is simplified using the properties of our FPGA (switch module structure and the number of routing resources). The routing algorithm is almost one hundred times faster than that of the conventional router, and the quality of its circuits is also improved.},
keywords={},
doi={},
ISSN={},
month={November},}
Copier
TY - JOUR
TI - Simplified Routing Procedure for a CAD-Verified FPGA
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2440
EP - 2447
AU - Takahiro MUROOKA
AU - Atsushi TAKAHARA
AU - Toshiaki MIYAZAKI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - The design of high performance-circuits using Field-Programmable Gate Arrays (FPGAs) requires a balance between the FPGA's architecture and CAD algorithms. Conventional FPGAs and CAD algorithms are developed independently, which makes it difficult to implement application circuits. To solve this problem, we developed a CAD-verified FPGA whose architecture was designed at the same time as the CAD algorithms. This paper shows how a CAD-verified FPGA architecture can simplify a routing algorithm. The algorithm is studied in terms of computational complexity and is simplified using the properties of our FPGA (switch module structure and the number of routing resources). The routing algorithm is almost one hundred times faster than that of the conventional router, and the quality of its circuits is also improved.
ER -