The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
La réduction de la taille du code est cruciale dans les systèmes embarqués ainsi que dans les systèmes hautes performances pour surmonter le goulot d'étranglement de communication entre la mémoire et le CPU, en particulier avec les processeurs VLIW (Very Long Instruction Word) qui nécessitent une prélecture des instructions à large bande passante. Cet article présente une nouvelle approche pour la compression de code basée sur un dictionnaire dans les systèmes basés sur un processeur VLIW utilisant l'isomorphisme entre les mots d'instruction. Après avoir divisé les mots d'instruction en deux groupes, l'un pour le groupe d'opcodes et l'autre pour le groupe d'opérandes, l'algorithme de compression proposé est appliqué à chaque groupe pour une compression maximale du code. Les mots d'instruction fréquemment utilisés sont extraits du code original pour être mappés dans deux dictionnaires, un dictionnaire d'opcodes et le dictionnaire d'opérandes. Selon les benchmarks SPEC95, la technique proposée a atteint un taux de compression de code moyen de 63 %, 69 % et 71 % dans une architecture VLIW à 4 numéros, 8 numéros et 12 numéros, respectivement.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Sang-Joon NAM, In-Cheol PARK, Chong-Min KYUNG, "Improving Dictionary-Based Code Compression in VLIW Architectures" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2318-2324, November 1999, doi: .
Abstract: Reducing code size is crucial in embedded systems as well as in high-performance systems to overcome the communication bottleneck between memory and CPU, especially with VLIW (Very Long Instruction Word) processors that require a high-bandwidth instruction prefetching. This paper presents a new approach for dictionary-based code compression in VLIW processor-based systems using isomorphism among instruction words. After we divide instruction words into two groups, one for opcode group and the other for operand group, the proposed compression algorithm is applied to each group for maximal code compression. Frequently-used instruction words are extracted from the original code to be mapped into two dictionaries, an opcode dictionary and an operand dictionary. According to the SPEC95 benchmarks, the proposed technique has achieved an average code compression ratio of 63%, 69%, and 71% in a 4-issue, 8-issue, and 12-issue VLIW architecture, respectively.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2318/_p
Copier
@ARTICLE{e82-a_11_2318,
author={Sang-Joon NAM, In-Cheol PARK, Chong-Min KYUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Improving Dictionary-Based Code Compression in VLIW Architectures},
year={1999},
volume={E82-A},
number={11},
pages={2318-2324},
abstract={Reducing code size is crucial in embedded systems as well as in high-performance systems to overcome the communication bottleneck between memory and CPU, especially with VLIW (Very Long Instruction Word) processors that require a high-bandwidth instruction prefetching. This paper presents a new approach for dictionary-based code compression in VLIW processor-based systems using isomorphism among instruction words. After we divide instruction words into two groups, one for opcode group and the other for operand group, the proposed compression algorithm is applied to each group for maximal code compression. Frequently-used instruction words are extracted from the original code to be mapped into two dictionaries, an opcode dictionary and an operand dictionary. According to the SPEC95 benchmarks, the proposed technique has achieved an average code compression ratio of 63%, 69%, and 71% in a 4-issue, 8-issue, and 12-issue VLIW architecture, respectively.},
keywords={},
doi={},
ISSN={},
month={November},}
Copier
TY - JOUR
TI - Improving Dictionary-Based Code Compression in VLIW Architectures
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2318
EP - 2324
AU - Sang-Joon NAM
AU - In-Cheol PARK
AU - Chong-Min KYUNG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - Reducing code size is crucial in embedded systems as well as in high-performance systems to overcome the communication bottleneck between memory and CPU, especially with VLIW (Very Long Instruction Word) processors that require a high-bandwidth instruction prefetching. This paper presents a new approach for dictionary-based code compression in VLIW processor-based systems using isomorphism among instruction words. After we divide instruction words into two groups, one for opcode group and the other for operand group, the proposed compression algorithm is applied to each group for maximal code compression. Frequently-used instruction words are extracted from the original code to be mapped into two dictionaries, an opcode dictionary and an operand dictionary. According to the SPEC95 benchmarks, the proposed technique has achieved an average code compression ratio of 63%, 69%, and 71% in a 4-issue, 8-issue, and 12-issue VLIW architecture, respectively.
ER -