The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose un système de synthèse de haut niveau pour la conception de chemins de données de matériels de traitement numérique. Le système se compose de quatre phases : (1) génération DFG (data-flow graph), (2) planification, (3) liaison de ressources et (4) génération HDL (langage de description matérielle). Dans (1), le système ne génère pas seulement un meilleur DFG représentant une description comportementale donnée d’un matériel, mais plusieurs bons DFG la représentant. En (2) et (3), plusieurs outils de synthèse peuvent être intégrés au système en fonction des objectifs recherchés. Ainsi, nous pouvons obtenir plus d'un chemin de données candidat pour une description comportementale avec leur zone et leur évaluation des performances. Dans (4), la meilleure conception de chemin de données est sélectionnée parmi ces candidats et sa description matérielle est générée. Les résultats expérimentaux pour l’application du système à plusieurs benchmarks montrent l’efficacité et l’efficience.
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Nozomu TOGAWA, Takafumi HISAKI, Masao YANAGISAWA, Tatsuo OHTSUKI, "A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2563-2575, December 1998, doi: .
Abstract: This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2563/_p
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@ARTICLE{e81-a_12_2563,
author={Nozomu TOGAWA, Takafumi HISAKI, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration},
year={1998},
volume={E81-A},
number={12},
pages={2563-2575},
abstract={This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2563
EP - 2575
AU - Nozomu TOGAWA
AU - Takafumi HISAKI
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.
ER -