The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article décrit un codec JPEG 158 à 2000 MS/s avec un codeur par blocs intégré (EBC) basé sur une architecture à plan binaire et à passes parallèles. L'EBC contient des codeurs de plan binaire (BPC) correspondant à chaque plan binaire dans un bloc de code. Les codages des plans de bits supérieur et inférieur se chevauchent dans le temps avec un espacement à 1 bande et à 1 colonne. Les passes de modélisation binaire dans le codage du plan binaire se chevauchent également dans le temps avec le même intervalle. Ces méthodes augmentent le débit de 30 fois par rapport aux méthodes conventionnelles. De plus, les procédés prennent en charge non seulement le mode causal vertical, mais également le mode régulier, qui améliore la qualité de l'image. De plus, un décodage spéculatif est adopté pour augmenter le débit. Ce codec LSI a été conçu selon un procédé de 0.18 µm. La zone centrale est de 4.7
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Masayuki MIYAMA, Yuusuke INOIE, Takafumi KASUGA, Ryouichi INADA, Masashi NAKAO, Yoshio MATSUDA, "A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 8, pp. 2025-2034, August 2008, doi: 10.1093/ietfec/e91-a.8.2025.
Abstract: This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 µm process. The core area is 4.7
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.8.2025/_p
Copier
@ARTICLE{e91-a_8_2025,
author={Masayuki MIYAMA, Yuusuke INOIE, Takafumi KASUGA, Ryouichi INADA, Masashi NAKAO, Yoshio MATSUDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission},
year={2008},
volume={E91-A},
number={8},
pages={2025-2034},
abstract={This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 µm process. The core area is 4.7
keywords={},
doi={10.1093/ietfec/e91-a.8.2025},
ISSN={1745-1337},
month={August},}
Copier
TY - JOUR
TI - A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2025
EP - 2034
AU - Masayuki MIYAMA
AU - Yuusuke INOIE
AU - Takafumi KASUGA
AU - Ryouichi INADA
AU - Masashi NAKAO
AU - Yoshio MATSUDA
PY - 2008
DO - 10.1093/ietfec/e91-a.8.2025
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2008
AB - This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 µm process. The core area is 4.7
ER -