The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article analyse le mécanisme interne des attaques par faute sur les microcontrôleurs et propose une politique de conception de contre-mesures matérielles et logicielles rentables. Des opérations de succursale fiables sont essentielles pour un matériel résistant à DFA. Notre méthode est basée sur une simulation d'attaque de faute logique pour trouver l'ensemble minimum de signaux qui contribuent aux fautes dans les opérations de branche et est également basée sur l'application d'une logique partiellement redondante.
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Masahiro KAMINAGA, Takashi WATANABE, Takashi ENDO, Toshio OKOCHI, "Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 7, pp. 1816-1819, July 2008, doi: 10.1093/ietfec/e91-a.7.1816.
Abstract: This article analyzes the internal mechanism of fault attacks on microcontrollers and proposes a cost-effective hardware and software countermeasure design policy. Reliable branch operations are essential to DFA-resistant hardware. Our method is based on a logical fault attack simulation to find the minimum set of signals that contribute to faults in the branch operations and is also based on applying partially redundant logic.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.7.1816/_p
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@ARTICLE{e91-a_7_1816,
author={Masahiro KAMINAGA, Takashi WATANABE, Takashi ENDO, Toshio OKOCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design},
year={2008},
volume={E91-A},
number={7},
pages={1816-1819},
abstract={This article analyzes the internal mechanism of fault attacks on microcontrollers and proposes a cost-effective hardware and software countermeasure design policy. Reliable branch operations are essential to DFA-resistant hardware. Our method is based on a logical fault attack simulation to find the minimum set of signals that contribute to faults in the branch operations and is also based on applying partially redundant logic.},
keywords={},
doi={10.1093/ietfec/e91-a.7.1816},
ISSN={1745-1337},
month={July},}
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TY - JOUR
TI - Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1816
EP - 1819
AU - Masahiro KAMINAGA
AU - Takashi WATANABE
AU - Takashi ENDO
AU - Toshio OKOCHI
PY - 2008
DO - 10.1093/ietfec/e91-a.7.1816
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2008
AB - This article analyzes the internal mechanism of fault attacks on microcontrollers and proposes a cost-effective hardware and software countermeasure design policy. Reliable branch operations are essential to DFA-resistant hardware. Our method is based on a logical fault attack simulation to find the minimum set of signals that contribute to faults in the branch operations and is also based on applying partially redundant logic.
ER -