The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Des recherches antérieures montrent que la politique de remplacement des LRU n'est pas efficace lorsque les applications présentent un intervalle de re-référence distant. Récemment, la politique RRIP a été proposée pour améliorer les performances pour ce type de charges de travail. Cependant, le manque d'informations sur la récence d'accès dans RRIP rend la politique de remplacement difficile à établir avec précision. Pour améliorer la robustesse de RRIP pour les charges de travail respectueuses de la récence, nous proposons une politique de prédiction dynamique d'insertion et de ré-référence adaptative (DAI-RRP) qui expulse les données en fonction à la fois de la valeur de prédiction de ré-référence et des informations de récence d'accès. DAI-RRP effectue un ajustement adaptatif de la position d'insertion et de la valeur de prédiction pour différents modèles d'accès, ce qui rend la politique robuste sur différentes charges de travail et différentes phases. Les résultats de simulation montrent que DAI-RRP surpasse LRU et RRIP. Pour un processeur monocœur doté d'un cache de dernier niveau (LLC) à 1 voies de 16 Mo, DAI-RRP réduit le CPI par rapport à LRU et Dynamic RRIP d'une moyenne de 8.1 % et 2.7 % respectivement. Les évaluations sur CMP quad-core avec un LLC partagé de 4 Mo montrent que DAI-RRP surpasse LRU et Dynamic RRIP (DRRIP) sur la métrique d'accélération pondérée d'une moyenne de 8.1 % et 15.7 % respectivement. De plus, par rapport à LRU, DAI-RRP consomme le même matériel pour le cache à 16 voies, voire moins de matériel pour le cache à haute associativité. En résumé, la politique proposée est pratique et peut être facilement intégrée aux approximations matérielles existantes de LRU.
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Xi ZHANG, Chongmin LI, Zhenyu LIU, Haixia WANG, Dongsheng WANG, Takeshi IKENAGA, "A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 468-476, April 2011, doi: 10.1587/transele.E94.C.468.
Abstract: Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1 MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4 MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.468/_p
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@ARTICLE{e94-c_4_468,
author={Xi ZHANG, Chongmin LI, Zhenyu LIU, Haixia WANG, Dongsheng WANG, Takeshi IKENAGA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction},
year={2011},
volume={E94-C},
number={4},
pages={468-476},
abstract={Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1 MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4 MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.},
keywords={},
doi={10.1587/transele.E94.C.468},
ISSN={1745-1353},
month={April},}
Copier
TY - JOUR
TI - A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction
T2 - IEICE TRANSACTIONS on Electronics
SP - 468
EP - 476
AU - Xi ZHANG
AU - Chongmin LI
AU - Zhenyu LIU
AU - Haixia WANG
AU - Dongsheng WANG
AU - Takeshi IKENAGA
PY - 2011
DO - 10.1587/transele.E94.C.468
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1 MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4 MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.
ER -