The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose un encodeur H.264 basé sur la région d'intérêt (ROI) et l'architecture VLSI de l'algorithme de détection de ROI. Dans un système de codage vidéo basé sur la ROI, l'unité de prétraitement destinée à détecter la ROI ne devrait introduire qu'une faible complexité de calcul en raison de la faible consommation d'énergie. Les macroblocs (MB) dans les ROI sont détectés séquentiellement dans le même ordre de codage H.264 pour satisfaire le pipeline de niveau MB du détecteur ROI et de l'encodeur H.264. La détection du retour sur investissement est effectuée dans un nouveau processus d'estimation et de vérification avec un modèle de contour de retour sur investissement. L'architecture proposée peut être configurée pour détecter une seule ROI ou plusieurs ROI dans chaque trame et le débit du mode de détection unique est 5.5 fois supérieur à celui du mode de détection multiple. 98.01 % et 97.89 % des Mo dans les ROI peuvent être détectés respectivement dans les modes de détection simple et multiple. Le coût matériel de l'architecture proposée n'est que de 4.68 753 portes. La vitesse de détection est de 200 ips pour la vidéo au format CIF à la fréquence de fonctionnement de 0.47 MHz en mode de détection multiple avec une consommation électrique de 264 mW. Par rapport aux précédents algorithmes de détection rapide du retour sur investissement pour les applications de codage vidéo, l'architecture proposée obtient un retour sur investissement plus précis et plus petit. Par conséquent, une complexité de calcul basée sur le retour sur investissement plus efficace et une optimisation de l'efficacité de la compression peuvent être mises en œuvre dans l'encodeur H.XNUMX.
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Tianruo ZHANG, Chen LIU, Minghui WANG, Satoshi GOTO, "Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 401-410, April 2011, doi: 10.1587/transele.E94.C.401.
Abstract: This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROI contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68 k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROI based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.401/_p
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@ARTICLE{e94-c_4_401,
author={Tianruo ZHANG, Chen LIU, Minghui WANG, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining},
year={2011},
volume={E94-C},
number={4},
pages={401-410},
abstract={This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROI contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68 k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROI based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.},
keywords={},
doi={10.1587/transele.E94.C.401},
ISSN={1745-1353},
month={April},}
Copier
TY - JOUR
TI - Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
T2 - IEICE TRANSACTIONS on Electronics
SP - 401
EP - 410
AU - Tianruo ZHANG
AU - Chen LIU
AU - Minghui WANG
AU - Satoshi GOTO
PY - 2011
DO - 10.1587/transele.E94.C.401
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROI contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68 k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROI based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.
ER -