The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nous avons conçu et implémenté un additionneur de retenue (CLA) à 4 bits et des multiplicateurs parallèles à 4 bits à utiliser pour le système de transformation de Fourier rapide (FFT) avec une fréquence d'horloge estimée à 20 GHz. Grâce à quelques tests fonctionnels à haute fréquence, nous avons confirmé que le fonctionnement du CLA a été réussi. A travers quelques tests à faible vitesse, nous avons également confirmé que l'opération de multiplication a réussi. De plus, nous avons conçu un multiplicateur 4 bits avec un encodeur Booth et un circuit papillon 2 points 4 bits.
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Ryosuke NAKAMOTO, Sakae SAKURABA, Alexandre MARTINS, Takeshi ONOMI, Shigeo SATO, Koji NAKAJIMA, "High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 3, pp. 280-287, March 2011, doi: 10.1587/transele.E94.C.280.
Abstract: We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.280/_p
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@ARTICLE{e94-c_3_280,
author={Ryosuke NAKAMOTO, Sakae SAKURABA, Alexandre MARTINS, Takeshi ONOMI, Shigeo SATO, Koji NAKAJIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform},
year={2011},
volume={E94-C},
number={3},
pages={280-287},
abstract={We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.},
keywords={},
doi={10.1587/transele.E94.C.280},
ISSN={1745-1353},
month={March},}
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TY - JOUR
TI - High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform
T2 - IEICE TRANSACTIONS on Electronics
SP - 280
EP - 287
AU - Ryosuke NAKAMOTO
AU - Sakae SAKURABA
AU - Alexandre MARTINS
AU - Takeshi ONOMI
AU - Shigeo SATO
AU - Koji NAKAJIMA
PY - 2011
DO - 10.1587/transele.E94.C.280
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2011
AB - We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.
ER -