The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'intégration élevée et le fonctionnement à faible consommation des circuits intégrés rendent la sensibilité au bruit élevée. Il est donc important de réduire le bruit des circuits. Un transconducteur à décalage de polarisation est appelé transconducteur linéaire. On s'attend à ce que la sensibilité au bruit du transconducteur devienne plus élevée en raison de l'amélioration de la linéarité et de la réduction de la dissipation de puissance. Cet article propose une méthode de conception pour réduire le bruit en tenant compte d'une linéarité élevée, d'une réduction de la dissipation de puissance et d'une petite taille de circuit.
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Shintaro NAKAMURA, Fujihiko MATSUMOTO, Pravit TONGPOON, Yasuaki NOGUCHI, "Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 1, pp. 128-131, January 2011, doi: 10.1587/transele.E94.C.128.
Abstract: High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.128/_p
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@ARTICLE{e94-c_1_128,
author={Shintaro NAKAMURA, Fujihiko MATSUMOTO, Pravit TONGPOON, Yasuaki NOGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor},
year={2011},
volume={E94-C},
number={1},
pages={128-131},
abstract={High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.},
keywords={},
doi={10.1587/transele.E94.C.128},
ISSN={1745-1353},
month={January},}
Copier
TY - JOUR
TI - Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor
T2 - IEICE TRANSACTIONS on Electronics
SP - 128
EP - 131
AU - Shintaro NAKAMURA
AU - Fujihiko MATSUMOTO
AU - Pravit TONGPOON
AU - Yasuaki NOGUCHI
PY - 2011
DO - 10.1587/transele.E94.C.128
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2011
AB - High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.
ER -