The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, un frontal analogique à très faible consommation pour les étiquettes RFID EPCglobal Classe 1 Génération 2 est présenté. L'étiquette RFID proposée supprime le besoin d'horloges et de compteurs haute fréquence utilisés dans les étiquettes conventionnelles, qui sont les blocs les plus gourmands en énergie. Le décodeur sans horloge proposé utilise un intégrateur analogique avec une source de courant adaptative qui fournit une marge de décodage uniforme quel que soit le débit de données et un extracteur de fréquence de liaison basé sur un oscillateur de relaxation qui génère la fréquence utilisée pour la rétrodiffusion. Un système de tension d'alimentation double est également utilisé pour augmenter l'efficacité énergétique de l'étiquette. Afin d'améliorer la tolérance du circuit proposé aux variations environnementales, un circuit d'auto-étalonnage est proposé. Le circuit frontal analogique RFID proposé est conçu et simulé en CMOS 0.25 µm, ce qui montre que la consommation d'énergie est réduite d'un ordre de grandeur par rapport aux étiquettes RFID conventionnelles, sans perdre l'immunité aux variations environnementales.
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Sung-Jin KIM, Minchang CHO, SeongHwan CHO, "An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 6, pp. 785-795, June 2010, doi: 10.1587/transele.E93.C.785.
Abstract: In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.785/_p
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@ARTICLE{e93-c_6_785,
author={Sung-Jin KIM, Minchang CHO, SeongHwan CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder},
year={2010},
volume={E93-C},
number={6},
pages={785-795},
abstract={In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.},
keywords={},
doi={10.1587/transele.E93.C.785},
ISSN={1745-1353},
month={June},}
Copier
TY - JOUR
TI - An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder
T2 - IEICE TRANSACTIONS on Electronics
SP - 785
EP - 795
AU - Sung-Jin KIM
AU - Minchang CHO
AU - SeongHwan CHO
PY - 2010
DO - 10.1587/transele.E93.C.785
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.
ER -