The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les excellentes performances du MOSFET vertical de type multi-nano-pilier (M-) à grille de 10 nm ont été démontrées numériquement pour la première fois. Il est clair que le MOSFET vertical M, par rapport au MOSFET vertical conventionnel de type à pilier unique (S-), a atteint un courant de commande accru de plus de 2 fois, un facteur S presque idéal et une coupure supprimée. courant de fuite de moins de 1/60 en supprimant à la fois l'effet canal court et l'effet DIBL. De plus, les mécanismes de ces améliorations du MOSFET M-Vertical sont clairement expliqués. De tout ce qui précède, il ressort que le MOSFET M-Vertical est un dispositif candidat clé pour les futurs LSI haute vitesse et faible consommation de la génération inférieure à 10 nm.
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Tetsuo ENDOH, Koji SAKUI, Yukio YASUDA, "Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 5, pp. 557-562, May 2010, doi: 10.1587/transele.E93.C.557.
Abstract: The excellent performance of the 10 nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10 nm generation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.557/_p
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@ARTICLE{e93-c_5_557,
author={Tetsuo ENDOH, Koji SAKUI, Yukio YASUDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET},
year={2010},
volume={E93-C},
number={5},
pages={557-562},
abstract={The excellent performance of the 10 nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10 nm generation.},
keywords={},
doi={10.1587/transele.E93.C.557},
ISSN={1745-1353},
month={May},}
Copier
TY - JOUR
TI - Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET
T2 - IEICE TRANSACTIONS on Electronics
SP - 557
EP - 562
AU - Tetsuo ENDOH
AU - Koji SAKUI
AU - Yukio YASUDA
PY - 2010
DO - 10.1587/transele.E93.C.557
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2010
AB - The excellent performance of the 10 nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10 nm generation.
ER -