The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Le convertisseur analogique-numérique (ADC) à approximation successive (SA) basé sur la redistribution des charges présente l'avantage d'une efficacité énergétique. La technique de convertisseur numérique-analogique à condensateur divisé (CDAC) met en œuvre deux ensembles de réseaux de condensateurs à pondération binaire connectés par un condensateur en pont de manière à réduire à la fois la capacité et la surface de la charge d'entrée. Cependant, les disparités de condensateurs dégradent les performances de l'ADC en termes de DNL et INL. Dans ce travail, une méthode d’étalonnage des mésappariements CDAC divisés est proposée. Un condensateur en pont plus grand que la conception conventionnelle est mis en œuvre de sorte qu'un condensateur accordable puisse être ajouté en parallèle avec le réseau de condensateurs de poids inférieur pour compenser les désadaptations. Pour garantir un étalonnage CDAC correct, le décalage du comparateur est annulé à l'aide d'une technique de compensation de charge à contrôle de synchronisation numérique. Pour réduire davantage la capacité de charge d'entrée, un condensateur unitaire supplémentaire est ajouté au réseau de condensateurs de poids plus élevé. Au lieu du réseau de condensateurs de poids inférieur, le condensateur unitaire supplémentaire et le réseau de condensateurs de poids plus élevé échantillonnent le signal d'entrée analogique. Un CAN SA 8 bits avec CDAC divisé 4 bits + 4 bits a été implémenté dans un processus CMOS 65 nm. L'ADC a une capacité d'entrée de 180 fF et occupe une zone active de 0.03 mm2. Des résultats mesurés de +0.2/-0.3LSB DNL et +0.3/-0.3LSB INL ont été obtenus après étalonnage.
Yanfei CHEN
Xiaolei ZHU
Hirotaka TAMURA
Masaya KIBUNE
Yasumoto TOMITA
Takayuki HAMADA
Masato YOSHIOKA
Kiyoshi ISHIKAWA
Takeshi TAKAYAMA
Junji OGAWA
Sanroku TSUKAMOTO
Tadahiro KURODA
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Yanfei CHEN, Xiaolei ZHU, Hirotaka TAMURA, Masaya KIBUNE, Yasumoto TOMITA, Takayuki HAMADA, Masato YOSHIOKA, Kiyoshi ISHIKAWA, Takeshi TAKAYAMA, Junji OGAWA, Sanroku TSUKAMOTO, Tadahiro KURODA, "Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 295-302, March 2010, doi: 10.1587/transele.E93.C.295.
Abstract: Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65 nm CMOS process. The ADC has an input capacitance of 180 fF and occupies an active area of 0.03 mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.295/_p
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@ARTICLE{e93-c_3_295,
author={Yanfei CHEN, Xiaolei ZHU, Hirotaka TAMURA, Masaya KIBUNE, Yasumoto TOMITA, Takayuki HAMADA, Masato YOSHIOKA, Kiyoshi ISHIKAWA, Takeshi TAKAYAMA, Junji OGAWA, Sanroku TSUKAMOTO, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC},
year={2010},
volume={E93-C},
number={3},
pages={295-302},
abstract={Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65 nm CMOS process. The ADC has an input capacitance of 180 fF and occupies an active area of 0.03 mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.},
keywords={},
doi={10.1587/transele.E93.C.295},
ISSN={1745-1353},
month={March},}
Copier
TY - JOUR
TI - Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC
T2 - IEICE TRANSACTIONS on Electronics
SP - 295
EP - 302
AU - Yanfei CHEN
AU - Xiaolei ZHU
AU - Hirotaka TAMURA
AU - Masaya KIBUNE
AU - Yasumoto TOMITA
AU - Takayuki HAMADA
AU - Masato YOSHIOKA
AU - Kiyoshi ISHIKAWA
AU - Takeshi TAKAYAMA
AU - Junji OGAWA
AU - Sanroku TSUKAMOTO
AU - Tadahiro KURODA
PY - 2010
DO - 10.1587/transele.E93.C.295
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65 nm CMOS process. The ADC has an input capacitance of 180 fF and occupies an active area of 0.03 mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.
ER -