The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Étant donné que les codes structurés de contrôle de parité à faible densité quasi-cyclique (QC-LDPC) pour la plupart des systèmes de communication sans fil modernes incluent plusieurs débits de code, différentes longueurs de bloc et les différentes tailles correspondantes de sous-matrices dans la matrice de contrôle de parité (PCM), le reconfigurable Le décodeur LDPC est souhaitable et le réseau de permutation est nécessaire pour prendre en charge tout numéro d'entrée (IN) et numéro de décalage (SN) pour le décalage cyclique. Dans cet article, nous proposons une nouvelle architecture de réseau de permutation pour les décodeurs reconfigurables QC-LDPC basés sur le réseau Banyan. Nous prouvons que le réseau Banyan a la propriété non bloquante de décalage cyclique lorsque l'IN est une puissance de 2, et donnons l'algorithme de génération du signal de commande. En introduisant le réseau de contournement, nous proposons un schéma non bloquant pour tous les IN et SN. De plus, nous présentons la conception matérielle du générateur de signaux de contrôle, qui peut réduire considérablement la complexité et la latence du matériel. Les résultats de synthèse utilisant la bibliothèque TSMC 0.18 µm démontrent que le réseau de permutation proposé peut être mis en œuvre avec une surface de 0.546 mm.2 et la fréquence de 292 MHz.
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Xiao PENG, Zhixiang CHEN, Xiongxin ZHAO, Fumiaki MAEHARA, Satoshi GOTO, "Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 270-278, March 2010, doi: 10.1587/transele.E93.C.270.
Abstract: Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18 µm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm2 and the frequency of 292 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.270/_p
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@ARTICLE{e93-c_3_270,
author={Xiao PENG, Zhixiang CHEN, Xiongxin ZHAO, Fumiaki MAEHARA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network},
year={2010},
volume={E93-C},
number={3},
pages={270-278},
abstract={Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18 µm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm2 and the frequency of 292 MHz.},
keywords={},
doi={10.1587/transele.E93.C.270},
ISSN={1745-1353},
month={March},}
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TY - JOUR
TI - Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
T2 - IEICE TRANSACTIONS on Electronics
SP - 270
EP - 278
AU - Xiao PENG
AU - Zhixiang CHEN
AU - Xiongxin ZHAO
AU - Fumiaki MAEHARA
AU - Satoshi GOTO
PY - 2010
DO - 10.1587/transele.E93.C.270
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18 µm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm2 and the frequency of 292 MHz.
ER -