The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un amplificateur différentiel à faible bruit (LNA) différentiel à large bande sub-GHz hautement intégré de hautes performances pour les applications de tuner de télévision numérique terrestre et par câble est réalisé en technologie CMOS de 0.18 µm. Une topologie de suppression de bruit utilisant un étage de source commune de réutilisation de courant à action directe est présentée pour obtenir des caractéristiques de faible bruit et un gain élevé tout en obtenant une bonne adaptation d'entrée à large bande dans la plage 48-860 MHz. De plus, les méthodes de linéarisation sont utilisées de manière appropriée pour améliorer la linéarité. Le LNA implémenté atteint un gain de puissance de 20.9 dB, un facteur de bruit minimum de 2.8 dB et un OIP3 de 24.2 dBm. La puce consomme 32 mA de courant avec une alimentation de 1.8 V et la taille de la puce est de 0.21 mm.2.
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Hyouk-Kyu CHA, "A CMOS Sub-GHz Wideband Low-Noise Amplifier for Digital TV Tuner Applications" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 1, pp. 142-144, January 2010, doi: 10.1587/transele.E93.C.142.
Abstract: A high performance highly integrated sub-GHz wideband differential low-noise amplifier (LNA) for terrestrial and cable digital TV tuner applications is realized in 0.18 µm CMOS technology. A noise-canceling topology using a feed-forward current reuse common-source stage is presented to obtain low noise characteristics and high gain while achieving good wideband input matching within 48-860 MHz. In addition, linearization methods are appropriately utilized to improve the linearity. The implemented LNA achieves a power gain of 20.9 dB, a minimum noise figure of 2.8 dB, and an OIP3 of 24.2 dBm. The chip consumes 32 mA of current at 1.8 V power supply and the core die size is 0.21 mm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.142/_p
Copier
@ARTICLE{e93-c_1_142,
author={Hyouk-Kyu CHA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A CMOS Sub-GHz Wideband Low-Noise Amplifier for Digital TV Tuner Applications},
year={2010},
volume={E93-C},
number={1},
pages={142-144},
abstract={A high performance highly integrated sub-GHz wideband differential low-noise amplifier (LNA) for terrestrial and cable digital TV tuner applications is realized in 0.18 µm CMOS technology. A noise-canceling topology using a feed-forward current reuse common-source stage is presented to obtain low noise characteristics and high gain while achieving good wideband input matching within 48-860 MHz. In addition, linearization methods are appropriately utilized to improve the linearity. The implemented LNA achieves a power gain of 20.9 dB, a minimum noise figure of 2.8 dB, and an OIP3 of 24.2 dBm. The chip consumes 32 mA of current at 1.8 V power supply and the core die size is 0.21 mm2.},
keywords={},
doi={10.1587/transele.E93.C.142},
ISSN={1745-1353},
month={January},}
Copier
TY - JOUR
TI - A CMOS Sub-GHz Wideband Low-Noise Amplifier for Digital TV Tuner Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 142
EP - 144
AU - Hyouk-Kyu CHA
PY - 2010
DO - 10.1587/transele.E93.C.142
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2010
AB - A high performance highly integrated sub-GHz wideband differential low-noise amplifier (LNA) for terrestrial and cable digital TV tuner applications is realized in 0.18 µm CMOS technology. A noise-canceling topology using a feed-forward current reuse common-source stage is presented to obtain low noise characteristics and high gain while achieving good wideband input matching within 48-860 MHz. In addition, linearization methods are appropriately utilized to improve the linearity. The implemented LNA achieves a power gain of 20.9 dB, a minimum noise figure of 2.8 dB, and an OIP3 of 24.2 dBm. The chip consumes 32 mA of current at 1.8 V power supply and the core die size is 0.21 mm2.
ER -