The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, nous présentons une nouvelle technique de conception de circuits à transistors composites qui améliore les performances des circuits analogiques. En ajoutant un transistor composite à l'amplificateur compensé en cascode, il a obtenu un gain CC de 102 dB et une bande passante de gain unitaire de 37.6 MHz tout en pilotant une lourde charge capacitive de 2 nF sur une seule alimentation de 1.8 V. Dans la comparaison des rendements puissance-bande passante et puissance-vitesse par rapport aux valeurs de mérite, il offre des valeurs significativement élevées par rapport aux travaux de pointe rapportés. En employant le transistor composite dans un régulateur linéaire alimenté par une alimentation de 3.3 V pour générer une tension de sortie de 1.8 V, il a montré une réponse de récupération rapide à divers transitoires de courant de charge, avec un temps de stabilisation de 1 % de 0.1 µS pour un courant de 50 mA ou 100 mA, tandis qu'un temps de stabilisation de 1 % de 0.36 µS pour un pas maximum de 735 mA sous une charge capacitive de 10 µF avec une résistance ESR de 1 Ω. La régulation de charge simulée est de 0.035 % et la régulation de ligne est de 0.488 %. En comparant ses résultats avec d'autres résultats rapportés par le LDO, il valide également les performances significativement améliorées de la conception proposée basée sur un transistor composite en termes de vitesse, de capacité de conduite actuelle et de stabilité face aux changements des paramètres environnementaux. Toutes les conceptions proposées sont simulées à l'aide d'une technologie de processus à triple puits CMOS à semi-conducteurs agréés (CSM) 1.8 V/3.3 V 0.18 µm avec des options d'oxyde mince/épais et des paramètres de modèle BSIM3.
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Yang TIAN, Pak Kwong CHAN, "Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 7, pp. 1199-1208, July 2010, doi: 10.1587/transele.E93.C.1199.
Abstract: In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1199/_p
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@ARTICLE{e93-c_7_1199,
author={Yang TIAN, Pak Kwong CHAN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors},
year={2010},
volume={E93-C},
number={7},
pages={1199-1208},
abstract={In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.},
keywords={},
doi={10.1587/transele.E93.C.1199},
ISSN={1745-1353},
month={July},}
Copier
TY - JOUR
TI - Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 1199
EP - 1208
AU - Yang TIAN
AU - Pak Kwong CHAN
PY - 2010
DO - 10.1587/transele.E93.C.1199
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2010
AB - In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.
ER -