The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une boucle à verrouillage de phase (PLL) à 2.5 phases de 8 GHz est proposée pour les applications de liaisons de transmission de système sur puce (SoC) à 10 Gbit/s. La PLL proposée possède plusieurs fonctionnalités qui utilisent de nouvelles techniques de conception. La première est une nouvelle cellule à retard variable (VDC) pour l'oscillateur à commande de tension (VCO). Ses avantages par rapport à la cellule à retard conventionnelle sont : une fréquence de sortie à large plage et une faible sensibilité au bruit avec un faible KVCO. La deuxième caractéristique est que la PLL se compose d'un circuit d'auto-étalonnage (SCC) qui protège la PLL des variations du processus, de la tension et de la température (PVT). La troisième caractéristique est que la PLL proposée a une fréquence de sortie à 8 phases et également, pour éviter l'effet puissance/terre (P/G) et l'effet de bruit du substrat sur la PLL, elle a également une faible fréquence de sortie de gigue. La PLL est implémentée en technologie CMOS 0.13 µm. La gigue de sortie PLL est de 2.83 ps (rms), soit moins de 0.7 % de la période de sortie. La dissipation de puissance totale est de 21 mW à une fréquence de sortie de 2.5 GHz et la zone centrale est de 0.08 mm.2.
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Kuo-Hsing CHENG, Yu-Chang TSAI, Chien-Nan Jimmy LIU, Kai-Wei HONG, Chin-Cheng KUO, "A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 7, pp. 964-972, July 2009, doi: 10.1587/transele.E92.C.964.
Abstract: A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.964/_p
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@ARTICLE{e92-c_7_964,
author={Kuo-Hsing CHENG, Yu-Chang TSAI, Chien-Nan Jimmy LIU, Kai-Wei HONG, Chin-Cheng KUO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application},
year={2009},
volume={E92-C},
number={7},
pages={964-972},
abstract={A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.},
keywords={},
doi={10.1587/transele.E92.C.964},
ISSN={1745-1353},
month={July},}
Copier
TY - JOUR
TI - A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 964
EP - 972
AU - Kuo-Hsing CHENG
AU - Yu-Chang TSAI
AU - Chien-Nan Jimmy LIU
AU - Kai-Wei HONG
AU - Chin-Cheng KUO
PY - 2009
DO - 10.1587/transele.E92.C.964
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2009
AB - A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.
ER -