The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un convertisseur analogique-numérique (A/D) de bande passante d'entrée de 1 GHz pour un récepteur radio à impulsions ultra-large bande (UWB-IR) est développé. Un circuit échantillonneur-bloqueur (S/H) sous-échantillonnage et un comparateur dynamique de réduction de courant sont proposés pour le convertisseur A/D. Un circuit S/H de sous-échantillonnage, qui numérise un signal d'entrée à une fréquence supérieure à la fréquence d'échantillonnage avec une faible consommation d'énergie, est nécessaire car le système UWB-IR utilise des impulsions ultracourtes intermittentes. Le circuit S/H proposé exécute l'échantillonnage en séparant un condensateur d'échantillonnage d'un amplificateur opérationnel et en accumulant la tension de décalage de l'amplificateur dans l'autre condensateur. Le comparateur de réduction de courant dynamique proposé réduit le courant de polarisation de manière dynamique correspondant à son niveau de tension d'entrée. Le convertisseur A/D est implémenté dans une technologie de traitement CMOS de 0.18 µm, qui atteint un nombre effectif de bits de 5.5, 5.4 et 4.9 pour les signaux d'entrée avec des fréquences de 1 513 et 1057 32 MHz, respectivement, à 0.89 M d'échantillons. /s. Le convertisseur consomme respectivement 0.42 mA et 1.8 mA dans les composants analogiques et numériques sur une alimentation de XNUMX V.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Tatsuo NAKAGAWA, Tatsuji MATSUURA, Eiki IMAIZUMI, Junya KUDOH, Goichi ONO, Masayuki MIYAZAKI, "1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 835-842, June 2009, doi: 10.1587/transele.E92.C.835.
Abstract: A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.835/_p
Copier
@ARTICLE{e92-c_6_835,
author={Tatsuo NAKAGAWA, Tatsuji MATSUURA, Eiki IMAIZUMI, Junya KUDOH, Goichi ONO, Masayuki MIYAZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver},
year={2009},
volume={E92-C},
number={6},
pages={835-842},
abstract={A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.},
keywords={},
doi={10.1587/transele.E92.C.835},
ISSN={1745-1353},
month={June},}
Copier
TY - JOUR
TI - 1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver
T2 - IEICE TRANSACTIONS on Electronics
SP - 835
EP - 842
AU - Tatsuo NAKAGAWA
AU - Tatsuji MATSUURA
AU - Eiki IMAIZUMI
AU - Junya KUDOH
AU - Goichi ONO
AU - Masayuki MIYAZAKI
PY - 2009
DO - 10.1587/transele.E92.C.835
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.
ER -