The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les progrès récents dans les technologies CMOS à grande échelle peuvent améliorer la bande passante du signal et la fréquence d'horloge des VLSI mixtes analogique-numérique. Cependant, la réduction inévitable de la tension d'alimentation provoque une inadéquation de tension de signal entre une puce analogique non mise à l'échelle et une puce mixte AD mise à l'échelle. Pour surmonter ce problème, nous présentons un amplificateur Delta (DeltAMP) capable de gérer une amplitude de signal plus grande que la tension d'alimentation. DeltaAMP replie un signal delta d'une tension d'entrée dans une fenêtre à l'aide d'un amplificateur de masse virtuel, de commutateurs de modulation et de comparateurs. Pour la reconstruction du signal delta plié en signal ordinal, une conversion analogique-temps-numérique (ATD) a également été proposée, dans laquelle les informations analogiques de largeur d'impulsion obtenues au niveau des comparateurs de DeltAMP ont été converties en un signal numérique par comptage. Une puce de test de DeltAMP avec ATD a été conçue et fabriquée à l'aide d'une technologie CMOS 90 nm. Une plage de tension d'entrée de 2 Vpp et une consommation électrique de 50 µW ont été obtenues grâce aux mesures avec une alimentation de 0.5 V. Une haute précision de 62 dB SNR a été obtenue avec une bande passante du signal de 120 kHz.
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Yoshihiro MASUI, Takeshi YOSHIDA, Atsushi IWATA, "A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 828-834, June 2009, doi: 10.1587/transele.E92.C.828.
Abstract: Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.828/_p
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@ARTICLE{e92-c_6_828,
author={Yoshihiro MASUI, Takeshi YOSHIDA, Atsushi IWATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion},
year={2009},
volume={E92-C},
number={6},
pages={828-834},
abstract={Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.},
keywords={},
doi={10.1587/transele.E92.C.828},
ISSN={1745-1353},
month={June},}
Copier
TY - JOUR
TI - A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion
T2 - IEICE TRANSACTIONS on Electronics
SP - 828
EP - 834
AU - Yoshihiro MASUI
AU - Takeshi YOSHIDA
AU - Atsushi IWATA
PY - 2009
DO - 10.1587/transele.E92.C.828
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.
ER -