The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente une nouvelle architecture pour augmenter l'utilisation du matériel dans les réseaux prédiffusés programmables sur site (MC-FPGA) multi-contextes. Les MC-FPGA conventionnels utilisent des pistes dédiées pour transférer les bits d'identification de contexte. En conséquence, le taux d’utilisation du matériel diminue, car il est très difficile de cartographier efficacement différents contextes et zones. Cela augmente également la puissance de commutation de contexte, la zone et la puissance statique des pistes d'identification de contexte. Le MC-FPGA proposé utilise les mêmes fils pour transférer à la fois les données et les bits d'identification de contexte d'une cellule à l'autre. En conséquence, les programmes peuvent être cartographiés efficacement en les divisant en différents contextes. Une architecture de blocs logiques multi-contextes asynchrones pour augmenter la vitesse de traitement des multiples contextes est également proposée. Le MC-FPGA proposé est fabriqué en utilisant les règles de conception CMOS 6-poly à 1 métaux. Les délais de transfert des données et des ID de contexte sont mesurés à 2.03ns 2.26ns respectivement. Nous avons obtenu une réduction de 30 % du temps de traitement pour l'algorithme de recherche de correspondance basé sur SAD.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, "Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 539-549, April 2009, doi: 10.1587/transele.E92.C.539.
Abstract: This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.539/_p
Copier
@ARTICLE{e92-c_4_539,
author={Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture},
year={2009},
volume={E92-C},
number={4},
pages={539-549},
abstract={This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.},
keywords={},
doi={10.1587/transele.E92.C.539},
ISSN={1745-1353},
month={April},}
Copier
TY - JOUR
TI - Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 539
EP - 549
AU - Hasitha Muthumala WAIDYASOORIYA
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2009
DO - 10.1587/transele.E92.C.539
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.
ER -