The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article décrit la méthodologie de modélisation et d'analyse pour évaluer le bruit de commutation simultanée (SSN) pour le système combiné du boîtier avec la carte de circuit imprimé (PCB) à 4 couches, dont les 64 sorties de commutation simultanées (SSO) ont été incluses à l'aide d'un simple Modèle IBIS. Les résultats de la simulation ont montré que le plan de masse du boîtier et du PCB peut être utilisé comme référence pour réduire le SSN plus efficacement que le plan d'alimentation. Pour la technique de synchronisation source synchrone telle que celle utilisée dans un bus mémoire DDR SDRAM dans le modèle présenté dans cet article, le circuit de contrôle d'inclinaison est facile à appliquer dans la conception de la puce au lieu d'utiliser des condensateurs intégrés dans le substrat du boîtier. L'émission rayonnée et l'analyse du diagramme oculaire ont également été étudiées.
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Narimasa TAKAHASHI, Kenji KAGAWA, Yutaka HONDA, Yo TAKAHASHI, "Simultaneous Switching Noise Analysis for High-Speed Interface" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 460-467, April 2009, doi: 10.1587/transele.E92.C.460.
Abstract: This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.460/_p
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@ARTICLE{e92-c_4_460,
author={Narimasa TAKAHASHI, Kenji KAGAWA, Yutaka HONDA, Yo TAKAHASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Simultaneous Switching Noise Analysis for High-Speed Interface},
year={2009},
volume={E92-C},
number={4},
pages={460-467},
abstract={This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.},
keywords={},
doi={10.1587/transele.E92.C.460},
ISSN={1745-1353},
month={April},}
Copier
TY - JOUR
TI - Simultaneous Switching Noise Analysis for High-Speed Interface
T2 - IEICE TRANSACTIONS on Electronics
SP - 460
EP - 467
AU - Narimasa TAKAHASHI
AU - Kenji KAGAWA
AU - Yutaka HONDA
AU - Yo TAKAHASHI
PY - 2009
DO - 10.1587/transele.E92.C.460
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.
ER -