The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article décrit la nouvelle architecture d'interface DDRx SDRAM adaptée à la mise en œuvre d'un système sur puce (SOC). Notre puce de test fabriquée selon un processus CMOS 90 nm adopte trois schémas clés et atteint des opérations de 960 Mb/s/broche avec une largeur de 32 bits. L'un des nouveaux schémas consiste à supprimer le décalage temporel à l'aide d'un circuit d'E/S de transmission de signal de front montant et d'un circuit d'étalonnage d'impédance de type table de correspondance. Le temps d'aller-retour DQS, le délai de propagation depuis le front montant de l'horloge système dans le SOC jusqu'à l'arrivée du DQS au PAD d'entrée du SOC pendant l'opération de lecture, devient supérieur à un temps de cycle d'horloge comme pour l'interface DDR2 et au-delà. Le schéma flexible de temps d'aller-retour DQS peut permettre une large plage allant jusqu'à N/2 cycles dans N opération de lecture en rafale de bits. De plus, un schéma de test entièrement auto-bouclé est également proposé pour mesurer les paramètres de synchronisation AC sans testeur haut de gamme. L'architecture présentée dans cet article peut s'adapter en permanence pour réaliser une interface DDRx-SDRAM à débit de données plus élevé et plus rentable pour différents types de SOC.
Masaru HARAGUCHI
Tokuya OSAWA
Akira YAMAZAKI
Chikayoshi MORISHIMA
Toshinori MORIHARA
Yoshikazu MOROOKA
Yoshihiro OKUNO
Kazutami ARIMOTO
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Copier
Masaru HARAGUCHI, Tokuya OSAWA, Akira YAMAZAKI, Chikayoshi MORISHIMA, Toshinori MORIHARA, Yoshikazu MOROOKA, Yoshihiro OKUNO, Kazutami ARIMOTO, "A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 453-459, April 2009, doi: 10.1587/transele.E92.C.453.
Abstract: This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.453/_p
Copier
@ARTICLE{e92-c_4_453,
author={Masaru HARAGUCHI, Tokuya OSAWA, Akira YAMAZAKI, Chikayoshi MORISHIMA, Toshinori MORIHARA, Yoshikazu MOROOKA, Yoshihiro OKUNO, Kazutami ARIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test},
year={2009},
volume={E92-C},
number={4},
pages={453-459},
abstract={This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.},
keywords={},
doi={10.1587/transele.E92.C.453},
ISSN={1745-1353},
month={April},}
Copier
TY - JOUR
TI - A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
T2 - IEICE TRANSACTIONS on Electronics
SP - 453
EP - 459
AU - Masaru HARAGUCHI
AU - Tokuya OSAWA
AU - Akira YAMAZAKI
AU - Chikayoshi MORISHIMA
AU - Toshinori MORIHARA
AU - Yoshikazu MOROOKA
AU - Yoshihiro OKUNO
AU - Kazutami ARIMOTO
PY - 2009
DO - 10.1587/transele.E92.C.453
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.
ER -