The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nous avons conçu une mémoire OTP (OTP) multibits asynchrone qui est utile pour les microunités de contrôle (MCU) des appareils mobiles généraux, des appareils automobiles, des circuits intégrés de puissance, des circuits intégrés d'affichage et des capteurs d'image CMOS. Une cellule OTP conventionnelle se compose d'un transistor d'accès, d'un condensateur NMOS comme antifusible et d'une diode NMOS mise à la terre pour la protection contre les décharges électrostatiques (ESD) afin de stocker un seul bit par cellule. Au contraire, une cellule OTP nouvellement proposée se compose d'un transistor de programme PMOS, d'un transistor de lecture NMOS, n Condensateurs NMOS comme antifusibles, et n Commutateurs NMOS sélectionnant l'antifusible à stocker n bits par cellule. Nous avons utilisé la tension d'alimentation logique VDD (=1.5 V) et une tension de programme externe VPPE (=8.5 V). En outre, nous avons simplifié le circuit de l'amplificateur de détection en utilisant l'amplificateur de détection de type inverseur cadencé [3] au lieu de l'amplificateur de détection de courant conventionnel [2]. L'OTP multi-bits asynchrone de 128 octets est conçu avec le processus CMOS Magnachip 0.13 µm. La zone de mise en page est 229.52
Chul-Ho CHOI
Jae-Hyung LEE
Tae-Hoon KIM
Oe-Yong SHIM
Yoon-Geum HWANG
Kwang-Seon AHN
Pan-Bong HA
Young-Hee KIM
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Chul-Ho CHOI, Jae-Hyung LEE, Tae-Hoon KIM, Oe-Yong SHIM, Yoon-Geum HWANG, Kwang-Seon AHN, Pan-Bong HA, Young-Hee KIM, "Design of Asynchronous Multi-Bit OTP Memory" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 1, pp. 173-177, January 2009, doi: 10.1587/transele.E92.C.173.
Abstract: We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.173/_p
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@ARTICLE{e92-c_1_173,
author={Chul-Ho CHOI, Jae-Hyung LEE, Tae-Hoon KIM, Oe-Yong SHIM, Yoon-Geum HWANG, Kwang-Seon AHN, Pan-Bong HA, Young-Hee KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Asynchronous Multi-Bit OTP Memory},
year={2009},
volume={E92-C},
number={1},
pages={173-177},
abstract={We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52
keywords={},
doi={10.1587/transele.E92.C.173},
ISSN={1745-1353},
month={January},}
Copier
TY - JOUR
TI - Design of Asynchronous Multi-Bit OTP Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 173
EP - 177
AU - Chul-Ho CHOI
AU - Jae-Hyung LEE
AU - Tae-Hoon KIM
AU - Oe-Yong SHIM
AU - Yoon-Geum HWANG
AU - Kwang-Seon AHN
AU - Pan-Bong HA
AU - Young-Hee KIM
PY - 2009
DO - 10.1587/transele.E92.C.173
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2009
AB - We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52
ER -