The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une nouvelle mémoire flash intégrée de 300 MHz pour microcontrôleurs double cœur avec une architecture ROM partagée est proposée. L'une de ses fonctionnalités est une opération de lecture de pipeline en trois étapes, qui permet de réduire le pas d'accès et donc de réduire les pénalités de performances dues aux conflits d'accès à la ROM partagée. Une autre caractéristique est un amplificateur de détection très sensible qui permet un fonctionnement efficace du pipeline avec un pas d'un cycle de latence à deux cycles grâce à un temps de détection raccourci de 0.63 ns. La combinaison de l'architecture pipeline et des amplificateurs de détection proposés réduit considérablement les pénalités de conflit d'accès avec la ROM partagée et améliore de 32 % les performances des microcontrôleurs double cœur RISC 30 bits.
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Shinya KAJIYAMA, Masamichi FUJITO, Hideo KASAI, Makoto MIZUNO, Takanori YAMAGUCHI, Yutaka SHINAGAWA, "A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 10, pp. 1258-1264, October 2009, doi: 10.1587/transele.E92.C.1258.
Abstract: A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1258/_p
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@ARTICLE{e92-c_10_1258,
author={Shinya KAJIYAMA, Masamichi FUJITO, Hideo KASAI, Makoto MIZUNO, Takanori YAMAGUCHI, Yutaka SHINAGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers},
year={2009},
volume={E92-C},
number={10},
pages={1258-1264},
abstract={A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.},
keywords={},
doi={10.1587/transele.E92.C.1258},
ISSN={1745-1353},
month={October},}
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TY - JOUR
TI - A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers
T2 - IEICE TRANSACTIONS on Electronics
SP - 1258
EP - 1264
AU - Shinya KAJIYAMA
AU - Masamichi FUJITO
AU - Hideo KASAI
AU - Makoto MIZUNO
AU - Takanori YAMAGUCHI
AU - Yutaka SHINAGAWA
PY - 2009
DO - 10.1587/transele.E92.C.1258
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.
ER -