The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Vues en texte intégral
75
Nous avons développé un circuit de niveau de tension autocontrôlable (SVL) et appliqué ce circuit à une mémoire vive statique (SRAM) à alimentation unique et à six transistors complémentaires à oxyde métallique et semi-conducteur pour non seulement améliorer les performances d'écriture et de lecture. mais également pour obtenir une faible consommation d'énergie en veille et une capacité de conservation (conservation) des données. Le circuit SVL ne comprend que trois MOSFET (c'est-à-dire des MOSFET pull-up, pull-down et bypass). Le circuit SVL est capable de générer de manière adaptative à la fois des tensions optimales de cellules de mémoire et des tensions de lignes de mots en fonction du mode de fonctionnement (c'est-à-dire une opération d'écriture, de lecture ou de maintien) qui a été utilisé. La marge d'écriture (VWM) et lire la marge (VRM) de la SRAM développée (dvlp) à une tension d'alimentation (VDD) de 1 V étaient respectivement de 0.470 et 0.1923 V. Ces valeurs étaient 1.309 et 2.093 fois VWM et VRM de la SRAM conventionnelle (conv), respectivement. À une tension de seuil élevée (Vt) variabilité (=+6σ), la tension d'alimentation minimale (VMin) pour l'opération d'écriture de la SRAM conv était de 0.37 V, alors qu'elle diminuait à 0.22 V pour la SRAM dvlp. VMin pour l'opération de lecture de la conv SRAM était de 1.05 V lorsque le Vt variabilité (=-6σ) était grand, mais la SRAM dvlp l'a abaissé à 0.41 V. Ces résultats montrent que le circuit SVL étend la plage de tension de fonctionnement pour les opérations d'écriture et de lecture jusqu'à abaisser les tensions. La SRAM dvlp réduit la consommation électrique en veille (PST) tout en conservant les données. Le mesuré PST de la SRAM dvlp 2 90 bits et 0.957 nm n'était que de XNUMXµW à VDD= 1.0 V, soit 9.46 % de PST de la conv SRAM (10.12µW). La surcharge de la zone Si des circuits SVL ne représentait que 1.383 % de la SRAM dvlp.
Tadayoshi ENOMOTO
Chuo University
Nobuaki KOBAYASHI
Nihon University
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, "Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 9, pp. 466-476, September 2023, doi: 10.1587/transele.2022ECP5053.
Abstract: We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022ECP5053/_p
Copier
@ARTICLE{e106-c_9_466,
author={Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption},
year={2023},
volume={E106-C},
number={9},
pages={466-476},
abstract={We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.},
keywords={},
doi={10.1587/transele.2022ECP5053},
ISSN={1745-1353},
month={September},}
Copier
TY - JOUR
TI - Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption
T2 - IEICE TRANSACTIONS on Electronics
SP - 466
EP - 476
AU - Tadayoshi ENOMOTO
AU - Nobuaki KOBAYASHI
PY - 2023
DO - 10.1587/transele.2022ECP5053
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2023
AB - We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.
ER -