The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose un pilote de modulation d'amplitude d'impulsion à quatre niveaux (pilote PAM-100) de faible consommation de 4 Gb/s, basé sur une structure de compensation de distorsion linéaire pour les modulateurs à couche mince de niobate de lithium (LiNbO3), qui parvient à atteindre une linéarité élevée de la sortie. La technologie de crête inductive et la structure à drain ouvert permettent à l'ensemble du circuit d'atteindre une bande passante de 31 GHz. D'une aire de 0.292 mm2, la puce pilote PAM-4 proposée est conçue selon un processus de 65 nm pour atteindre une consommation d'énergie de 37.7 mW. Les résultats de simulation post-mise en page montrent que l'efficacité énergétique est de 0.37 mW/Gb/s, le RLM est supérieur à 96 % et la valeur FOM est de 8.84.
Xiangyu MENG
Sun Yat-sen University
Kangfeng WEI
Sun Yat-sen University
Zhiyi YU
Sun Yat-sen University
Xinlun CAI
Sun Yat-sen University
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Xiangyu MENG, Kangfeng WEI, Zhiyi YU, Xinlun CAI, "A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 1, pp. 7-13, January 2023, doi: 10.1587/transele.2022ECP5010.
Abstract: This paper proposes a low-power 100Gb/s four-level pulse amplitude modulation driver (PAM-4 Driver) based on linear distortion compensation structure for thin-film Lithium Niobate (LiNbO3) modulators, which manages to achieve high linearity in the output. The inductive peaking technology and open drain structure enable the overall circuit to achieve a 31-GHz bandwidth. With an area of 0.292 mm2, the proposed PAM-4 driver chip is designed in a 65-nm process to achieve power consumption of 37.7 mW. Post-layout simulation results show that the power efficiency is 0.37 mW/Gb/s, RLM is more than 96%, and the FOM value is 8.84.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022ECP5010/_p
Copier
@ARTICLE{e106-c_1_7,
author={Xiangyu MENG, Kangfeng WEI, Zhiyi YU, Xinlun CAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS},
year={2023},
volume={E106-C},
number={1},
pages={7-13},
abstract={This paper proposes a low-power 100Gb/s four-level pulse amplitude modulation driver (PAM-4 Driver) based on linear distortion compensation structure for thin-film Lithium Niobate (LiNbO3) modulators, which manages to achieve high linearity in the output. The inductive peaking technology and open drain structure enable the overall circuit to achieve a 31-GHz bandwidth. With an area of 0.292 mm2, the proposed PAM-4 driver chip is designed in a 65-nm process to achieve power consumption of 37.7 mW. Post-layout simulation results show that the power efficiency is 0.37 mW/Gb/s, RLM is more than 96%, and the FOM value is 8.84.},
keywords={},
doi={10.1587/transele.2022ECP5010},
ISSN={1745-1353},
month={January},}
Copier
TY - JOUR
TI - A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 7
EP - 13
AU - Xiangyu MENG
AU - Kangfeng WEI
AU - Zhiyi YU
AU - Xinlun CAI
PY - 2023
DO - 10.1587/transele.2022ECP5010
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2023
AB - This paper proposes a low-power 100Gb/s four-level pulse amplitude modulation driver (PAM-4 Driver) based on linear distortion compensation structure for thin-film Lithium Niobate (LiNbO3) modulators, which manages to achieve high linearity in the output. The inductive peaking technology and open drain structure enable the overall circuit to achieve a 31-GHz bandwidth. With an area of 0.292 mm2, the proposed PAM-4 driver chip is designed in a 65-nm process to achieve power consumption of 37.7 mW. Post-layout simulation results show that the power efficiency is 0.37 mW/Gb/s, RLM is more than 96%, and the FOM value is 8.84.
ER -