The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
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La sécurité et la confiance matérielles dans les puces de circuits intégrés (CI) à semi-conducteurs sont très demandées. Cet article décrit les exigences et les développements récents en matière de circuits et de systèmes de conditionnement de puces IC pour les applications de sécurité, avec un accent particulier sur les protections contre les attaques d'implémentation physique. Les canaux côté alimentation sont d'une présence indésirable pour les circuits cryptographiques une fois qu'un algorithme cryptographique est implémenté dans le silicium, sur les réseaux de distribution d'énergie (PDN) sur la face avant d'une puce ou même à travers la face arrière d'un substrat Si, sous la forme d'une variation de tension d'alimentation et émanation d'ondes électromagnétiques. Des mesures préventives ont été exploitées avec des technologies de conception de circuits et de conditionnement, et en partie démontrées avec des véhicules d'essai Si.
Makoto NAGATA
Graduate School of Science, Technology and Innovation, Kobe University
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Makoto NAGATA, "Design of Circuits and Packaging Systems for Security Chips" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 7, pp. 345-351, July 2023, doi: 10.1587/transele.2022CDI0001.
Abstract: Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CDI0001/_p
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@ARTICLE{e106-c_7_345,
author={Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Circuits and Packaging Systems for Security Chips},
year={2023},
volume={E106-C},
number={7},
pages={345-351},
abstract={Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.},
keywords={},
doi={10.1587/transele.2022CDI0001},
ISSN={1745-1353},
month={July},}
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TY - JOUR
TI - Design of Circuits and Packaging Systems for Security Chips
T2 - IEICE TRANSACTIONS on Electronics
SP - 345
EP - 351
AU - Makoto NAGATA
PY - 2023
DO - 10.1587/transele.2022CDI0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2023
AB - Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.
ER -