The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
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106
Une unité arithmétique et logique (ALU) de 32 bits est conçue pour un processeur bit-parallèle rapide quantique à flux unique (RSFQ). Dans l'ALU, les portails cadencés sont partiellement remplacés par des portails sans horloge. Cela réduit le nombre de bascules D (DFF) requises pour l'équilibrage du chemin. Le nombre de portes cadencées, y compris les DFF, est réduit d'environ 40 % et la taille du réseau de distribution d'horloge est réduite. Le nombre d'étapes du pipeline devient modeste. La conception de l'agencement de l'ALU et les résultats de simulation montrent l'efficacité de l'utilisation de portes sans horloge dans des circuits à chemin de données large.
Takahiro KAWAGUCHI
Kyoto University
Naofumi TAKAGI
Kyoto University
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Takahiro KAWAGUCHI, Naofumi TAKAGI, "32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor" in IEICE TRANSACTIONS on Electronics,
vol. E105-C, no. 6, pp. 245-250, June 2022, doi: 10.1587/transele.2021SEP0005.
Abstract: A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021SEP0005/_p
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@ARTICLE{e105-c_6_245,
author={Takahiro KAWAGUCHI, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor},
year={2022},
volume={E105-C},
number={6},
pages={245-250},
abstract={A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.},
keywords={},
doi={10.1587/transele.2021SEP0005},
ISSN={1745-1353},
month={June},}
Copier
TY - JOUR
TI - 32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 245
EP - 250
AU - Takahiro KAWAGUCHI
AU - Naofumi TAKAGI
PY - 2022
DO - 10.1587/transele.2021SEP0005
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2022
AB - A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.
ER -