The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente plusieurs techniques de conception pour améliorer les performances des multiplicateurs de fréquence CMOS qui fonctionnent dans la bande sub-THz sans augmenter la complexité et la consommation d'énergie du circuit. Les techniques proposées sont appliquées à un tripleur de fréquence basé sur la non-linéarité et à un doubleur de fréquence push-push. En utilisant l'annulation du retour d'harmonique fondamentale et de seconde harmonique, le tripleur atteint une puissance de sortie de -2.9 dBm avec une architecture de circuit simple à une extrémité réduisant la surface requise et la consommation d'énergie. Le tripleur fonctionne à des fréquences de 103 GHz à 130 GHz. Le doubleur push-push modifié introduit offre un gain de conversion de 2.3 dB, y compris les pertes du balun, et présente une bonne tolérance aux inadéquations du balun. La fréquence de sortie du doubleur est de 118 GHz à 124 GHz. Les deux circuits ont été conçus et fabriqués à l’aide de la technologie CMOS 65 nm.
Ibrahim ABDO
Tokyo Institute of Technology
Korkut Kaan TOKGOZ
Tokyo Institute of Technology
Atsushi SHIRANE
Tokyo Institute of Technology
Kenichi OKADA
Tokyo Institute of Technology
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Ibrahim ABDO, Korkut Kaan TOKGOZ, Atsushi SHIRANE, Kenichi OKADA, "F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power" in IEICE TRANSACTIONS on Electronics,
vol. E105-C, no. 3, pp. 118-125, March 2022, doi: 10.1587/transele.2021ECP5036.
Abstract: This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021ECP5036/_p
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@ARTICLE{e105-c_3_118,
author={Ibrahim ABDO, Korkut Kaan TOKGOZ, Atsushi SHIRANE, Kenichi OKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power},
year={2022},
volume={E105-C},
number={3},
pages={118-125},
abstract={This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.},
keywords={},
doi={10.1587/transele.2021ECP5036},
ISSN={1745-1353},
month={March},}
Copier
TY - JOUR
TI - F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power
T2 - IEICE TRANSACTIONS on Electronics
SP - 118
EP - 125
AU - Ibrahim ABDO
AU - Korkut Kaan TOKGOZ
AU - Atsushi SHIRANE
AU - Kenichi OKADA
PY - 2022
DO - 10.1587/transele.2021ECP5036
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2022
AB - This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.
ER -