The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les performances d’un routeur/switch réseau se sont considérablement améliorées au cours des dernières décennies avec une augmentation explosive du trafic Internet et des centres de données. Les performances d'un routeur dépendent fortement du système de mémoire, par exemple des tampons de paquets basés sur la DRAM, ce qui limite souvent l'évolutivité d'un routeur. Cependant, un écart croissant entre la vitesse du bus d'E/S mémoire et du réseau de cellules mémoire et une diminution de la localité du tampon de ligne due à l'augmentation des canaux et des banques réduisent considérablement le gain de performances de la technologie de mémoire de pointe telle que la DRAM DDR4 ou HBM2. Des travaux antérieurs ont amélioré la bande passante mémoire en maintenant des tampons d'entrée/sortie par file d'attente ou par banque basés sur la SRAM dans le contrôleur de mémoire pour prendre en charge un tampon de paquets basé sur la DRAM. Les tampons stockent temporairement les paquets lorsque des conflits bancaires se produisent, mais sont incapables d'empêcher le trafic induisant des interférences de détruire les tampons de lignes de la DRAM. Dans cette étude, nous intégrons directement la SRAM dans le tampon de paquets basé sur la DRAM et mappons les paquets dégradant la localité du tampon de ligne de la DRAM dans la SRAM. Cela maximise la localité et le parallélisme des accès DRAM. Le régime proposé peut bénéficier à tous les régimes existants. Les résultats expérimentaux montrent une amélioration de 22.41 % par rapport au meilleur schéma existant pour un seul canal en termes d'utilisation de la bande passante mémoire dans des scénarios d'encombrement sévères.
Yongwoon SONG
Sogang University
Dongkeon CHOI
Sogang University
Hyukjun LEE
Sogang University
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Yongwoon SONG, Dongkeon CHOI, Hyukjun LEE, "Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 12, pp. 849-852, December 2019, doi: 10.1587/transele.2019ECS6003.
Abstract: The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECS6003/_p
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@ARTICLE{e102-c_12_849,
author={Yongwoon SONG, Dongkeon CHOI, Hyukjun LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers},
year={2019},
volume={E102-C},
number={12},
pages={849-852},
abstract={The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.},
keywords={},
doi={10.1587/transele.2019ECS6003},
ISSN={1745-1353},
month={December},}
Copier
TY - JOUR
TI - Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers
T2 - IEICE TRANSACTIONS on Electronics
SP - 849
EP - 852
AU - Yongwoon SONG
AU - Dongkeon CHOI
AU - Hyukjun LEE
PY - 2019
DO - 10.1587/transele.2019ECS6003
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2019
AB - The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.
ER -