The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
En ce qui concerne la taille élargie du réseau pour les nouveaux émetteurs-récepteurs à réseau phasé à ondes millimétriques radio (NR) 5G, une résolution de réglage de phase améliorée sera nécessaire pour prendre en charge le contrôle précis du faisceau. Cet article présente une implémentation CMOS d'un déphaseur à sommation vectorielle active. Le déphaseur proposé réalise un déphasage de 6 bits avec une zone active de 0.32 mm2. Pour minimiser la variation de gain lors de l'accord de phase, une technique de compensation d'erreur de gain est proposée. Après compensation, la variation de gain mesurée dans la bande 5G NR n257 est inférieure à 0.9 dB. L'erreur de gain RMS correspondante est inférieure à 0.2 dB. L'erreur de phase RMS mesurée de 26.5 GHz à 29.5 GHz est inférieure à 1.2°. Ce travail réalise un réglage de phase à haute résolution et invariant le gain. Compte tenu des performances de l'ampleur du vecteur d'erreur (EVM), le déphaseur proposé prend en charge un débit de données maximum de 11.2 Gb/s en 256QAM avec une consommation électrique de 25.2 mW.
Jian PANG
Tokyo Institute of Technology
Ryo KUBOZOE
Tokyo Institute of Technology
Zheng LI
Tokyo Institute of Technology
Masaru KAWABUCHI
Tokyo Institute of Technology
Atsushi SHIRANE
Tokyo Institute of Technology
Kenichi OKADA
Tokyo Institute of Technology
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Jian PANG, Ryo KUBOZOE, Zheng LI, Masaru KAWABUCHI, Atsushi SHIRANE, Kenichi OKADA, "A 28-GHz CMOS Vector-Summing Phase Shifter Featuring I/Q Imbalance Calibration Supporting 11.2Gb/s in 256QAM for 5G New Radio" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 2, pp. 39-47, February 2020, doi: 10.1587/transele.2019ECP5017.
Abstract: Regarding the enlarged array size for the 5G new radio (NR) millimeter-wave phased-array transceivers, an improved phase tuning resolution will be required to support the accurate beam control. This paper introduces a CMOS implementation of an active vector-summing phase shifter. The proposed phase shifter realizes a 6-bit phase shifting with an active area of 0.32mm2. To minimize the gain variation during the phase tuning, a gain error compensation technique is proposed. After the compensation, the measured gain variation within the 5G NR band n257 is less than 0.9dB. The corresponding RMS gain error is less than 0.2dB. The measured RMS phase error from 26.5GHz to 29.5GHz is less than 1.2°. Gain-invariant, high-resolution phase tuning is realized by this work. Considering the error vector magnitude (EVM) performance, the proposed phase shifter supports a maximum data rate of 11.2Gb/s in 256QAM with a power consumption of 25.2mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECP5017/_p
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@ARTICLE{e103-c_2_39,
author={Jian PANG, Ryo KUBOZOE, Zheng LI, Masaru KAWABUCHI, Atsushi SHIRANE, Kenichi OKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 28-GHz CMOS Vector-Summing Phase Shifter Featuring I/Q Imbalance Calibration Supporting 11.2Gb/s in 256QAM for 5G New Radio},
year={2020},
volume={E103-C},
number={2},
pages={39-47},
abstract={Regarding the enlarged array size for the 5G new radio (NR) millimeter-wave phased-array transceivers, an improved phase tuning resolution will be required to support the accurate beam control. This paper introduces a CMOS implementation of an active vector-summing phase shifter. The proposed phase shifter realizes a 6-bit phase shifting with an active area of 0.32mm2. To minimize the gain variation during the phase tuning, a gain error compensation technique is proposed. After the compensation, the measured gain variation within the 5G NR band n257 is less than 0.9dB. The corresponding RMS gain error is less than 0.2dB. The measured RMS phase error from 26.5GHz to 29.5GHz is less than 1.2°. Gain-invariant, high-resolution phase tuning is realized by this work. Considering the error vector magnitude (EVM) performance, the proposed phase shifter supports a maximum data rate of 11.2Gb/s in 256QAM with a power consumption of 25.2mW.},
keywords={},
doi={10.1587/transele.2019ECP5017},
ISSN={1745-1353},
month={February},}
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TY - JOUR
TI - A 28-GHz CMOS Vector-Summing Phase Shifter Featuring I/Q Imbalance Calibration Supporting 11.2Gb/s in 256QAM for 5G New Radio
T2 - IEICE TRANSACTIONS on Electronics
SP - 39
EP - 47
AU - Jian PANG
AU - Ryo KUBOZOE
AU - Zheng LI
AU - Masaru KAWABUCHI
AU - Atsushi SHIRANE
AU - Kenichi OKADA
PY - 2020
DO - 10.1587/transele.2019ECP5017
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2020
AB - Regarding the enlarged array size for the 5G new radio (NR) millimeter-wave phased-array transceivers, an improved phase tuning resolution will be required to support the accurate beam control. This paper introduces a CMOS implementation of an active vector-summing phase shifter. The proposed phase shifter realizes a 6-bit phase shifting with an active area of 0.32mm2. To minimize the gain variation during the phase tuning, a gain error compensation technique is proposed. After the compensation, the measured gain variation within the 5G NR band n257 is less than 0.9dB. The corresponding RMS gain error is less than 0.2dB. The measured RMS phase error from 26.5GHz to 29.5GHz is less than 1.2°. Gain-invariant, high-resolution phase tuning is realized by this work. Considering the error vector magnitude (EVM) performance, the proposed phase shifter supports a maximum data rate of 11.2Gb/s in 256QAM with a power consumption of 25.2mW.
ER -