The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article traite de l'impact de l'empilement d'inducteurs sur puce sur le réseau d'alimentation/terre. L'empilement d'inductances sur d'autres composants du circuit peut réduire considérablement la surface du circuit. Cependant, l'impact sur l'intégrité du signal et de l'alimentation n'est pas clair. Nous étudions l'impact à l'aide d'un solveur de champ, d'un simulateur de circuit et de mesures réelles de puces. Nous évaluons trois types de réseaux puissance/terre et diverses inductances multicouches. Les résultats expérimentaux montrent que les structures denses puissance/terre réduisent le bruit bien que la capacité de couplage devienne plus grande que celle des structures clairsemées. La mesure dans un CMOS 65 nm montre qu'une structure tissée réduit la tension de bruit de moitié par rapport à une structure clairsemée.
Akira TSUCHIYA
The University of Shiga Prefecture
Akitaka HIRATSUKA
Kyoto University
Toshiyuki INOUE
The University of Shiga Prefecture
Keiji KISHINE
The University of Shiga Prefecture
Hidetoshi ONODERA
Kyoto University
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Akira TSUCHIYA, Akitaka HIRATSUKA, Toshiyuki INOUE, Keiji KISHINE, Hidetoshi ONODERA, "Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 7, pp. 573-579, July 2019, doi: 10.1587/transele.2018CTP0007.
Abstract: This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018CTP0007/_p
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@ARTICLE{e102-c_7_573,
author={Akira TSUCHIYA, Akitaka HIRATSUKA, Toshiyuki INOUE, Keiji KISHINE, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity},
year={2019},
volume={E102-C},
number={7},
pages={573-579},
abstract={This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.},
keywords={},
doi={10.1587/transele.2018CTP0007},
ISSN={1745-1353},
month={July},}
Copier
TY - JOUR
TI - Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity
T2 - IEICE TRANSACTIONS on Electronics
SP - 573
EP - 579
AU - Akira TSUCHIYA
AU - Akitaka HIRATSUKA
AU - Toshiyuki INOUE
AU - Keiji KISHINE
AU - Hidetoshi ONODERA
PY - 2019
DO - 10.1587/transele.2018CTP0007
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2019
AB - This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.
ER -