The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les erreurs logicielles mettent en péril la fiabilité des dispositifs à semi-conducteurs, en particulier ceux fonctionnant à basse tension. Ces dernières années, le silicium sur boîtier mince (SOTB), qui est un dispositif FD-SOI, a attiré l'attention car il convient au fonctionnement à très basse tension. Ce travail évalue les contributions de la SRAM, du FF et du circuit combinatoire au taux d'erreur logicielle (SER) au niveau de la puce, sur la base des résultats des tests d'irradiation. Pour cette évaluation, ce travail a effectué un test d'irradiation neutronique pour caractériser le taux de transitoire à événement unique (SET) des circuits SOTB et de masse à 0.5 V. En utilisant les données SBU et MCU dans les SRAM de travaux précédents, nous avons calculé le taux MBU avec/sans correction d'erreur. code (ECC) et avec entrelacement MUX 1/2/4-col. En combinant les taux d'erreur FF rapportés dans la littérature, nous avons estimé le SER au niveau de la puce et chaque contribution au SER au niveau de la puce pour les processeurs embarqués et hautes performances. Pour les deux processeurs, sans ECC, 95 % d'erreurs se produisent au niveau de la SRAM dans les puces SOTB et en vrac à 0.5 V et 1.0 V, et les SER globaux au niveau de la puce SOTB supposée à 0.5 V sont au moins 10 fois inférieurs à cela. de copeaux en vrac. D'un autre côté, lorsque l'ECC est appliqué à la SRAM dans la puce SOTB, les SEU apparaissant au niveau des FF sont dominants dans le processeur haute performance, tandis que les MBU dans les SRAM ne sont pas négligeables dans les puces embarquées en masse.
Wang LIAO
Osaka University
Masanori HASHIMOTO
Osaka University
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Wang LIAO, Masanori HASHIMOTO, "Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 4, pp. 296-302, April 2019, doi: 10.1587/transele.2018CDP0004.
Abstract: Soft error jeopardizes the reliability of semiconductor devices, especially those working at low voltage. In recent years, silicon-on-thin-box (SOTB), which is a FD-SOI device, is drawing attention since it is suitable for ultra-low-voltage operation. This work evaluates the contributions of SRAM, FF and combinational circuit to chip-level soft error rate (SER) based on irradiation test results. For this evaluation, this work performed neutron irradiation test for characterizing single event transient (SET) rate of SOTB and bulk circuits at 0.5 V. Using the SBU and MCU data in SRAMs from previous work, we calculated the MBU rate with/without error correcting code (ECC) and with 1/2/4-col MUX interleaving. Combining FF error rates reported in literature, we estimated chip-level SER and each contribution to chip-level SER for embedded and high-performance processors. For both the processors, without ECC, 95% errors occur at SRAM in both SOTB and bulk chips at 0.5 V and 1.0 V, and the overall chip-level SERs of the assumed SOTB chip at 0.5 V is at least 10 x lower than that of bulk chip. On the other hand, when ECC is applied to SRAM in the SOTB chip, SEUs occurring at FFs are dominant in the high-performance processor while MBUs at SRAMs are not negligible in the bulk embedded chips.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018CDP0004/_p
Copier
@ARTICLE{e102-c_4_296,
author={Wang LIAO, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate},
year={2019},
volume={E102-C},
number={4},
pages={296-302},
abstract={Soft error jeopardizes the reliability of semiconductor devices, especially those working at low voltage. In recent years, silicon-on-thin-box (SOTB), which is a FD-SOI device, is drawing attention since it is suitable for ultra-low-voltage operation. This work evaluates the contributions of SRAM, FF and combinational circuit to chip-level soft error rate (SER) based on irradiation test results. For this evaluation, this work performed neutron irradiation test for characterizing single event transient (SET) rate of SOTB and bulk circuits at 0.5 V. Using the SBU and MCU data in SRAMs from previous work, we calculated the MBU rate with/without error correcting code (ECC) and with 1/2/4-col MUX interleaving. Combining FF error rates reported in literature, we estimated chip-level SER and each contribution to chip-level SER for embedded and high-performance processors. For both the processors, without ECC, 95% errors occur at SRAM in both SOTB and bulk chips at 0.5 V and 1.0 V, and the overall chip-level SERs of the assumed SOTB chip at 0.5 V is at least 10 x lower than that of bulk chip. On the other hand, when ECC is applied to SRAM in the SOTB chip, SEUs occurring at FFs are dominant in the high-performance processor while MBUs at SRAMs are not negligible in the bulk embedded chips.},
keywords={},
doi={10.1587/transele.2018CDP0004},
ISSN={1745-1353},
month={April},}
Copier
TY - JOUR
TI - Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate
T2 - IEICE TRANSACTIONS on Electronics
SP - 296
EP - 302
AU - Wang LIAO
AU - Masanori HASHIMOTO
PY - 2019
DO - 10.1587/transele.2018CDP0004
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2019
AB - Soft error jeopardizes the reliability of semiconductor devices, especially those working at low voltage. In recent years, silicon-on-thin-box (SOTB), which is a FD-SOI device, is drawing attention since it is suitable for ultra-low-voltage operation. This work evaluates the contributions of SRAM, FF and combinational circuit to chip-level soft error rate (SER) based on irradiation test results. For this evaluation, this work performed neutron irradiation test for characterizing single event transient (SET) rate of SOTB and bulk circuits at 0.5 V. Using the SBU and MCU data in SRAMs from previous work, we calculated the MBU rate with/without error correcting code (ECC) and with 1/2/4-col MUX interleaving. Combining FF error rates reported in literature, we estimated chip-level SER and each contribution to chip-level SER for embedded and high-performance processors. For both the processors, without ECC, 95% errors occur at SRAM in both SOTB and bulk chips at 0.5 V and 1.0 V, and the overall chip-level SERs of the assumed SOTB chip at 0.5 V is at least 10 x lower than that of bulk chip. On the other hand, when ECC is applied to SRAM in the SOTB chip, SEUs occurring at FFs are dominant in the high-performance processor while MBUs at SRAMs are not negligible in the bulk embedded chips.
ER -