The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, une nouvelle méthode de réduction de la traversée d'horloge dans des amplificateurs opérationnels CMOS à zéro automatique avec fonctionnement d'horloge triphasé est présentée. Les amplificateurs opérationnels du procédé sont configurés par deux étages de gain à mise à zéro automatique. L'étage d'entrée différentiel et le deuxième étage de gain de sortie sont mis à zéro automatiquement individuellement par une horloge triphasée pour la mise à zéro automatique. L'horloge triphasée est prévue de manière à terminer la période de compensation de l'étage d'entrée avant la fin de la période de compensation du deuxième étage. Cette opération permet d'absorber l'affection du passage d'horloge dans l'étage d'entrée avec le deuxième étage. En conséquence, l'erreur résiduelle de compensation de décalage est considérablement réduite par le gain de tension du premier étage. L'effet de la mise à zéro automatique en deux étapes a été confirmé par la simulation SPICE et le circuit CMOS fabriqué. Les résultats de la simulation SPICE ont montré que l'amplificateur opérationnel à deux étages avec mise à zéro automatique présente un avantage significatif par rapport à la configuration conventionnelle. L'effet du passage d'horloge est réduit à environ 1/50 dans la configuration à deux étages. Le circuit CMOS fabriqué a également montré le potentiel élevé de l'amplificateur opérationnel à mise à zéro automatique à deux étages pour la réduction de la traversée. Il a été prouvé expérimentalement que la mise à zéro automatique en deux étapes constitue une approche de conception efficace pour réduire les erreurs de transmission d'horloge dans les amplificateurs opérationnels à mise à zéro automatique CMOS.
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Hidekuni TAKAO, Fumie INA, Kazuaki SAWADA, Makoto ISHIDA, "Clock Feedthrough Reduction of CMOS Autozeroed Operational Amplifiers by Two-Stage Self-Compensation" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 7, pp. 1499-1505, July 2002, doi: .
Abstract: In this paper, a novel method of clock feedthrough reduction in CMOS autozeroed operational amplifiers with three-phase clock operation is presented. The operational amplifiers in the method are configured by two autozeroed-gain stages. The differential input stage and the second output gain stage are autozeroed individually by a three-phase clock for autozeroing. The three-phase clock is provided so as to finish the compensation period of the input stage earlier than the end of the second stage compensation period. This operation makes it possible to absorb affection of clock feedthrough in the input stage with the second stage. As a result, residual error of offset compensation is much reduced by the voltage gain of the first stage. The effect of the two-stage autozeroing has been confirmed with SPICE simulation and fabricated CMOS circuit. The results of SPICE simulation showed that the two-stage autozeroed operational amplifier has significant advantage as compared to conventional configuration. Affection of clock feedthrough is reduced to about 1/50 in the two-stage configuration. Fabricated CMOS circuit also showed high potential of the two-stage autozeroed operational amplifier for feedthrough reduction. It has been proven experimentally that the two-stage autozeroing is an effective design approach to reduce clock feedthrough error in CMOS autozeroed operational amplifiers.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_7_1499/_p
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@ARTICLE{e85-c_7_1499,
author={Hidekuni TAKAO, Fumie INA, Kazuaki SAWADA, Makoto ISHIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Clock Feedthrough Reduction of CMOS Autozeroed Operational Amplifiers by Two-Stage Self-Compensation},
year={2002},
volume={E85-C},
number={7},
pages={1499-1505},
abstract={In this paper, a novel method of clock feedthrough reduction in CMOS autozeroed operational amplifiers with three-phase clock operation is presented. The operational amplifiers in the method are configured by two autozeroed-gain stages. The differential input stage and the second output gain stage are autozeroed individually by a three-phase clock for autozeroing. The three-phase clock is provided so as to finish the compensation period of the input stage earlier than the end of the second stage compensation period. This operation makes it possible to absorb affection of clock feedthrough in the input stage with the second stage. As a result, residual error of offset compensation is much reduced by the voltage gain of the first stage. The effect of the two-stage autozeroing has been confirmed with SPICE simulation and fabricated CMOS circuit. The results of SPICE simulation showed that the two-stage autozeroed operational amplifier has significant advantage as compared to conventional configuration. Affection of clock feedthrough is reduced to about 1/50 in the two-stage configuration. Fabricated CMOS circuit also showed high potential of the two-stage autozeroed operational amplifier for feedthrough reduction. It has been proven experimentally that the two-stage autozeroing is an effective design approach to reduce clock feedthrough error in CMOS autozeroed operational amplifiers.},
keywords={},
doi={},
ISSN={},
month={July},}
Copier
TY - JOUR
TI - Clock Feedthrough Reduction of CMOS Autozeroed Operational Amplifiers by Two-Stage Self-Compensation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1499
EP - 1505
AU - Hidekuni TAKAO
AU - Fumie INA
AU - Kazuaki SAWADA
AU - Makoto ISHIDA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2002
AB - In this paper, a novel method of clock feedthrough reduction in CMOS autozeroed operational amplifiers with three-phase clock operation is presented. The operational amplifiers in the method are configured by two autozeroed-gain stages. The differential input stage and the second output gain stage are autozeroed individually by a three-phase clock for autozeroing. The three-phase clock is provided so as to finish the compensation period of the input stage earlier than the end of the second stage compensation period. This operation makes it possible to absorb affection of clock feedthrough in the input stage with the second stage. As a result, residual error of offset compensation is much reduced by the voltage gain of the first stage. The effect of the two-stage autozeroing has been confirmed with SPICE simulation and fabricated CMOS circuit. The results of SPICE simulation showed that the two-stage autozeroed operational amplifier has significant advantage as compared to conventional configuration. Affection of clock feedthrough is reduced to about 1/50 in the two-stage configuration. Fabricated CMOS circuit also showed high potential of the two-stage autozeroed operational amplifier for feedthrough reduction. It has been proven experimentally that the two-stage autozeroing is an effective design approach to reduce clock feedthrough error in CMOS autozeroed operational amplifiers.
ER -