The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article décrit le comportement non linéaire de la capacité d'entrée du CAN CMOS. Notre simulation SPICE, basée sur le modèle BSIM3v3, montre que la capacité d'entrée d'un CAN de type flash CMOS typique (avec un préamplificateur à paire différentielle NMOS asymétrique comme étage d'entrée) diminue à mesure que sa tension d'entrée augmente ; c'est le contraire de ce à quoi nous nous attendrions si nous considérions uniquement la non-linéarité de la capacité de la grille MOSFET. Nous avons constaté que cela peut s'expliquer par la non-linéarité de la capacité d'entrée effective totale de chaque étage amplificateur différentiel, en tenant compte non seulement de la capacité MOSFET mais également du fait que les contributions des capacités grille-source et grille-drain à l'entrée la capacité de la paire différentielle change en fonction de ses tensions d'entrée (une tension d'entrée ADC et une tension de référence). Nous discutons également des méthodes de conception permettant de réduire la valeur de la capacité d'entrée effective du CAN CMOS.
Hideyuki KOGURE
Haruo KOBAYASHI
Yuuichi TAKAHASHI
Takao MYONO
Hiroyuki SATO
Yasuyuki KIMURA
Yoshitaka ONAYA
Kouji TANAKA
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Hideyuki KOGURE, Haruo KOBAYASHI, Yuuichi TAKAHASHI, Takao MYONO, Hiroyuki SATO, Yasuyuki KIMURA, Yoshitaka ONAYA, Kouji TANAKA, "Analysis of CMOS ADC Nonlinear Input Capacitance" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1182-1190, May 2002, doi: .
Abstract: This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1182/_p
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@ARTICLE{e85-c_5_1182,
author={Hideyuki KOGURE, Haruo KOBAYASHI, Yuuichi TAKAHASHI, Takao MYONO, Hiroyuki SATO, Yasuyuki KIMURA, Yoshitaka ONAYA, Kouji TANAKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Analysis of CMOS ADC Nonlinear Input Capacitance},
year={2002},
volume={E85-C},
number={5},
pages={1182-1190},
abstract={This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.},
keywords={},
doi={},
ISSN={},
month={May},}
Copier
TY - JOUR
TI - Analysis of CMOS ADC Nonlinear Input Capacitance
T2 - IEICE TRANSACTIONS on Electronics
SP - 1182
EP - 1190
AU - Hideyuki KOGURE
AU - Haruo KOBAYASHI
AU - Yuuichi TAKAHASHI
AU - Takao MYONO
AU - Hiroyuki SATO
AU - Yasuyuki KIMURA
AU - Yoshitaka ONAYA
AU - Kouji TANAKA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.
ER -