The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nous avons développé une méthode d'analyse de la pénétration du bore et de l'épuisement des portes en utilisant N+ et P+ PMOSFET à double porte. Un N+ Les PMOSFET à grille, qui sont immunisés contre la pénétration du bore et l'épuisement de la grille, présentaient des changements de tension de seuil et des fluctuations de P+ PMOSFET à porte fabriqués en utilisant un N identique- substrats. Nous avons montré l'importance de Vth analyse des fluctuations et a constaté que le Vth fluctuation de N+ Les PMOSFET de porte étaient négligeables, mais le Vth fluctuation de P+ Les PMOSFET de porte étaient significatifs, indiquant que le Vth fluctuation de P+ Les PMOSFET à grille étaient dominés par la pénétration du bore. Il a également été démontré, pour la première fois, que la pénétration du bore se produisait avec l'épuisement des grilles, et que l'épuisement des grilles devait être très fort pour supprimer la pénétration du bore. La méthode PMOSFET à double porte permet de sélectionner des processus de fabrication de DRAM G-bit hautes performances, robustes contre Vth fluctuation.
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Norikatsu TAKAURA, Ryo NAGAI, Hisao ASAKURA, Satoru YAMADA, Shin'ichiro KIMURA, "Analysis of Boron Penetration and Gate Depletion Using Dual-Gate PMOSFETs for High Performance G-Bit DRAM Design" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1138-1145, May 2002, doi: .
Abstract: We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1138/_p
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@ARTICLE{e85-c_5_1138,
author={Norikatsu TAKAURA, Ryo NAGAI, Hisao ASAKURA, Satoru YAMADA, Shin'ichiro KIMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Analysis of Boron Penetration and Gate Depletion Using Dual-Gate PMOSFETs for High Performance G-Bit DRAM Design},
year={2002},
volume={E85-C},
number={5},
pages={1138-1145},
abstract={We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.},
keywords={},
doi={},
ISSN={},
month={May},}
Copier
TY - JOUR
TI - Analysis of Boron Penetration and Gate Depletion Using Dual-Gate PMOSFETs for High Performance G-Bit DRAM Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 1138
EP - 1145
AU - Norikatsu TAKAURA
AU - Ryo NAGAI
AU - Hisao ASAKURA
AU - Satoru YAMADA
AU - Shin'ichiro KIMURA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.
ER -