The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nous avons proposé le MOSFET à canal parallèle triangulaire haute densité sur un substrat SOI et avons démontré les effets de canal court supprimés par simulation et expérience. Dans cette structure de dispositif, le processus de fabrication est entièrement compatible avec le processus MOSFET planaire et est beaucoup moins compliqué que d'autres structures de dispositif non plan, notamment les MOSFET à grille complète (GAA) et SOI à double grille. De plus, notre processus de fabrication permet de doubler la densité des fils, ce qui entraîne un courant d'entraînement plus élevé. Les résultats de la simulation tridimensionnelle montrent que le MOSFET à canal filaire triangulaire proposé présente de meilleures caractéristiques de canal court que les MOSFET SOI à simple et double grille. Les MOSFET à canal métallique parallèle triangulaire fabriqués présentent de meilleures caractéristiques inférieures au seuil et moins d'abaissement de barrière induit par le drain (DIBL) que les MOSFET SOI à grille unique.
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Toshiki SAITO, Takuya SARAYA, Takashi INUKAI, Hideaki MAJIMA, Toshiharu NAGUMO, Toshiro HIRAMOTO, "Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1073-1078, May 2002, doi: .
Abstract: We have proposed the high-density triangular parallel wire channel MOSFET on an SOI substrate and demonstrated the suppressed short channel effects by simulation and experiment. In this device structure, the fabrication process is fully compatible with the planar MOSFET process and is much less complicated than other non-planer device structures including gate-all-around (GAA) and double-gate SOI MOSFETs. In addition, our fabrication process makes it possible to double the wire density resulting in the higher current drive. The three-dimensional simulation results show that the proposed triangular wire channel MOSFET has better short channel characteristics than single-gate and double-gate SOI MOSFETs. The fabricated triangular parallel wire channel MOSFETs show better subthreshold characteristics and less drain induced barrier lowering (DIBL) than the single-gate SOI MOSFETs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1073/_p
Copier
@ARTICLE{e85-c_5_1073,
author={Toshiki SAITO, Takuya SARAYA, Takashi INUKAI, Hideaki MAJIMA, Toshiharu NAGUMO, Toshiro HIRAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs},
year={2002},
volume={E85-C},
number={5},
pages={1073-1078},
abstract={We have proposed the high-density triangular parallel wire channel MOSFET on an SOI substrate and demonstrated the suppressed short channel effects by simulation and experiment. In this device structure, the fabrication process is fully compatible with the planar MOSFET process and is much less complicated than other non-planer device structures including gate-all-around (GAA) and double-gate SOI MOSFETs. In addition, our fabrication process makes it possible to double the wire density resulting in the higher current drive. The three-dimensional simulation results show that the proposed triangular wire channel MOSFET has better short channel characteristics than single-gate and double-gate SOI MOSFETs. The fabricated triangular parallel wire channel MOSFETs show better subthreshold characteristics and less drain induced barrier lowering (DIBL) than the single-gate SOI MOSFETs.},
keywords={},
doi={},
ISSN={},
month={May},}
Copier
TY - JOUR
TI - Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1073
EP - 1078
AU - Toshiki SAITO
AU - Takuya SARAYA
AU - Takashi INUKAI
AU - Hideaki MAJIMA
AU - Toshiharu NAGUMO
AU - Toshiro HIRAMOTO
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - We have proposed the high-density triangular parallel wire channel MOSFET on an SOI substrate and demonstrated the suppressed short channel effects by simulation and experiment. In this device structure, the fabrication process is fully compatible with the planar MOSFET process and is much less complicated than other non-planer device structures including gate-all-around (GAA) and double-gate SOI MOSFETs. In addition, our fabrication process makes it possible to double the wire density resulting in the higher current drive. The three-dimensional simulation results show that the proposed triangular wire channel MOSFET has better short channel characteristics than single-gate and double-gate SOI MOSFETs. The fabricated triangular parallel wire channel MOSFETs show better subthreshold characteristics and less drain induced barrier lowering (DIBL) than the single-gate SOI MOSFETs.
ER -