The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un encodeur DRAM MPEG-64 LSI intégré de 2 Mo sur puce avec un processeur multimédia a été développé. Pour mettre en œuvre ce LSI à grande échelle et à grande vitesse, nous avons développé le contrôle hiérarchique du biais des multi-horloges, avec vérification du timing, dans lequel le bruit de diaphonie est pris en compte, et des mesures simples prises contre la chute IR dans les lignes électriques via condensateurs de découplage. En conséquence, la performance cible de 263 MHz à 1.5 V a été atteinte et vérifiée avec succès, le bruit de diaphonie a été pris en compte et, en outre, il est devenu possible de limiter la chute IR à 166 mV dans la bande de 162 MHz. bloc d’opération.
Hidehiro TAKATA
Rei AKIYAMA
Tadao YAMANAKA
Haruyuki OHKUMA
Yasue SUETSUGU
Toshihiro KANAOKA
Satoshi KUMAKI
Kazuya ISHIHARA
Atsuo HANAMI
Tetsuya MATSUMURA
Tetsuya WATANABE
Yoshihide AJIOKA
Yoshio MATSUDA
Syuhei IWADE
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Hidehiro TAKATA, Rei AKIYAMA, Tadao YAMANAKA, Haruyuki OHKUMA, Yasue SUETSUGU, Toshihiro KANAOKA, Satoshi KUMAKI, Kazuya ISHIHARA, Atsuo HANAMI, Tetsuya MATSUMURA, Tetsuya WATANABE, Yoshihide AJIOKA, Yoshio MATSUDA, Syuhei IWADE, "Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 368-374, February 2002, doi: .
Abstract: An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_368/_p
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@ARTICLE{e85-c_2_368,
author={Hidehiro TAKATA, Rei AKIYAMA, Tadao YAMANAKA, Haruyuki OHKUMA, Yasue SUETSUGU, Toshihiro KANAOKA, Satoshi KUMAKI, Kazuya ISHIHARA, Atsuo HANAMI, Tetsuya MATSUMURA, Tetsuya WATANABE, Yoshihide AJIOKA, Yoshio MATSUDA, Syuhei IWADE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor},
year={2002},
volume={E85-C},
number={2},
pages={368-374},
abstract={An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.},
keywords={},
doi={},
ISSN={},
month={February},}
Copier
TY - JOUR
TI - Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 368
EP - 374
AU - Hidehiro TAKATA
AU - Rei AKIYAMA
AU - Tadao YAMANAKA
AU - Haruyuki OHKUMA
AU - Yasue SUETSUGU
AU - Toshihiro KANAOKA
AU - Satoshi KUMAKI
AU - Kazuya ISHIHARA
AU - Atsuo HANAMI
AU - Tetsuya MATSUMURA
AU - Tetsuya WATANABE
AU - Yoshihide AJIOKA
AU - Yoshio MATSUDA
AU - Syuhei IWADE
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.
ER -