The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose une violation constructive du timing (CTV) et évalue son potentiel. Il peut être utilisé à la fois pour augmenter la fréquence d’horloge et pour réduire la consommation d’énergie. L'augmentation de la fréquence d'horloge au-delà de celle déterminée par les chemins critiques entraîne des violations de synchronisation. D'un autre côté, même si la réduction de la tension d'alimentation peut entraîner des économies d'énergie substantielles, elle entraîne également un retard de grille plus important et l'horloge doit donc être ralentie afin de ne pas violer les contraintes de synchronisation des chemins critiques. Cependant, si des mécanismes de tolérance sont prévus pour les violations de timing, il n'est pas nécessaire de conserver les contraintes. Les violations seraient plutôt constructives pour une fréquence d’horloge élevée ou pour des économies d’énergie. A partir de ces observations, nous proposons le CTV, qui s'appuie sur le mécanisme tolérant basé sur les mécanismes d'exécution spéculative contemporains. Nous évaluons le CTV à l'aide d'un simulateur cycle par cycle et présentons son potentiel considérablement prometteur.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Toshinori SATO, Itsujiro ARITA, "Potential of Constructive Timing-Violation" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 323-330, February 2002, doi: .
Abstract: This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_323/_p
Copier
@ARTICLE{e85-c_2_323,
author={Toshinori SATO, Itsujiro ARITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Potential of Constructive Timing-Violation},
year={2002},
volume={E85-C},
number={2},
pages={323-330},
abstract={This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.},
keywords={},
doi={},
ISSN={},
month={February},}
Copier
TY - JOUR
TI - Potential of Constructive Timing-Violation
T2 - IEICE TRANSACTIONS on Electronics
SP - 323
EP - 330
AU - Toshinori SATO
AU - Itsujiro ARITA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.
ER -