The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un cœur de microprocesseur RISC intégré de 32 bits intégrant un DSP a été développé à l'aide d'une technologie CMOS métallique à cinq couches de 0.18 µm. Le DSP intégré dispose d'un seul MAC et exploite les ressources du processeur pour réduire le matériel. Le DSP occupe seulement 0.5 mm2. Le cœur du processeur comprend une grande SRAM intégrée de 128 Ko appelée mémoire U. Une mémoire sur puce de grande capacité réduit la quantité de trafic avec une mémoire externe. Et il est efficace pour un fonctionnement à faible consommation et hautes performances. Afin d'obtenir une faible dissipation de puissance pour l'accès à la mémoire U, le rapport actif d'accès à la mémoire U est réduit. Le chemin critique est un chemin de charge à partir de la mémoire U, et nous avons optimisé le chemin à travers l'ensemble de la puce. La puce atteint 0.79 mA/MHz en exécutant Dhrystone 1.1 à 108 MHz, ce qui convient aux applications mobiles.
Tetsuya YAMADA
Makoto ISHIKAWA
Yuji OGATA
Takanobu TSUNODA
Takahiro IRITA
Saneaki TAMAKI
Kunihiko NISHIYAMA
Tatsuya KAMEI
Ken TATEZAWA
Fumio ARAKAWA
Takuichiro NAKAZAWA
Toshihiro HATTORI
Kunio UCHIYAMA
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Tetsuya YAMADA, Makoto ISHIKAWA, Yuji OGATA, Takanobu TSUNODA, Takahiro IRITA, Saneaki TAMAKI, Kunihiko NISHIYAMA, Tatsuya KAMEI, Ken TATEZAWA, Fumio ARAKAWA, Takuichiro NAKAZAWA, Toshihiro HATTORI, Kunio UCHIYAMA, "A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 253-262, February 2002, doi: .
Abstract: A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-µm five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm2. The processor core includes a large on-chip 128 kB SRAM called U-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_253/_p
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@ARTICLE{e85-c_2_253,
author={Tetsuya YAMADA, Makoto ISHIKAWA, Yuji OGATA, Takanobu TSUNODA, Takahiro IRITA, Saneaki TAMAKI, Kunihiko NISHIYAMA, Tatsuya KAMEI, Ken TATEZAWA, Fumio ARAKAWA, Takuichiro NAKAZAWA, Toshihiro HATTORI, Kunio UCHIYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications},
year={2002},
volume={E85-C},
number={2},
pages={253-262},
abstract={A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-µm five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm2. The processor core includes a large on-chip 128 kB SRAM called U-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.},
keywords={},
doi={},
ISSN={},
month={February},}
Copier
TY - JOUR
TI - A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 253
EP - 262
AU - Tetsuya YAMADA
AU - Makoto ISHIKAWA
AU - Yuji OGATA
AU - Takanobu TSUNODA
AU - Takahiro IRITA
AU - Saneaki TAMAKI
AU - Kunihiko NISHIYAMA
AU - Tatsuya KAMEI
AU - Ken TATEZAWA
AU - Fumio ARAKAWA
AU - Takuichiro NAKAZAWA
AU - Toshihiro HATTORI
AU - Kunio UCHIYAMA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-µm five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm2. The processor core includes a large on-chip 128 kB SRAM called U-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.
ER -